[Bug target/111376] missed optimization of one bit test on MIPS32r1

["syq at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111376

--- Comment #5 from YunQiang Su <syq at gcc dot gnu.org> ---
I copy the RTL pattern from RISC-V, and it seems work

```
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -6253,6 +6253,40 @@ (define_insn "*branch_bit<bbv><mode>_inverted"
 }
   [(set_attr "type"         "branch")
    (set_attr "branch_likely" "no")])
+
+(define_insn_and_split "*branch_on_bit<mode>"
+  [(set (pc)
+       (if_then_else
+           (match_operator 0 "equality_operator"
+               [(zero_extract:GPR (match_operand:GPR 2 "register_operand" "d")
+                                (const_int 1)
+                                (match_operand:GPR 3 "const_int_operand"))
+                                (const_int 0)])
+           (label_ref (match_operand 1))
+           (pc)))]
+  "!ISA_HAS_BBIT && !ISA_HAS_EXT_INS && !TARGET_MIPS16"
+  "#"
+  "!reload_completed"
+  [(set (match_dup 4)
+       (ashift:GPR (match_dup 2) (match_dup 3)))
+   (set (pc)
+       (if_then_else
+           (match_op_dup 0 [(match_dup 4) (const_int 0)])
+           (label_ref (match_operand 1))
+           (pc)))]
+{
+  int shift = GET_MODE_BITSIZE (<MODE>mode) - 1 - INTVAL (operands[3]);
+  operands[3] = GEN_INT (shift);
+  operands[4] = gen_reg_rtx (<MODE>mode);
+
+  if (GET_CODE (operands[0]) == EQ)
+    operands[0] = gen_rtx_GE (<MODE>mode, operands[4], const0_rtx);
+  else
+    operands[0] = gen_rtx_LT (<MODE>mode, operands[4], const0_rtx);
+}
+[(set_attr "type" "branch")])
+
+
```