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From: "syq at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug target/111376] missed optimization of one bit test on MIPS32r1
Date: Sat, 15 Jun 2024 06:47:06 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D111376

--- Comment #13 from YunQiang Su <syq at gcc dot gnu.org> ---
I try to insert=20
        li      $3, 500
        li      $5, 500
between SLL/BGEZ  and LUI+AND/BNE.

The later is still some faster on Loongson 3A4000.

I notice something like this in 74K's software manual:

The 74K core=E2=80=99s ALU is pipelined. Some ALU instructions complete the=
 operation
and bypass the results in this cycle. These instructions are referred to as
single-cycle ops and they include all logical instructions (AND, ANDI, OR, =
ORI,
XOR, XORI, LUI), some shift instructions (SLL sa<=3D8, SRL 31<=3Dsa<=3D25),=
 and some
arithmetic instructions (ADD rt=3D0, ADDU rt=3D0, SLT, SLTI, SLTU, SLTIU, S=
EH, SEB,
ZEH, ZEB). In addition, add instructions (ADD, ADDU, ADDI, ADDIU) complete =
the
operation and bypass results to the ALU pipe in this cycle.


I guess it means that if sa>8, SLL may be some slow.
On Loongson 3A4000, the value seems to be 20/21. It may means that we shoul=
d be
care about for 64bit.

Can you have a test on XBurst 1?=