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From: "lis8215 at gmail dot com" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug rtl-optimization/111376] New: missed optimization of one bit
 test on MIPS32r1
Date: Mon, 11 Sep 2023 18:24:57 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D111376

            Bug ID: 111376
           Summary: missed optimization of one bit test on MIPS32r1
           Product: gcc
           Version: unknown
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: rtl-optimization
          Assignee: unassigned at gcc dot gnu.org
          Reporter: lis8215 at gmail dot com
  Target Milestone: ---

Created attachment 55879
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=3D55879&action=3Dedit
Silly patch to enable SLL+BLTZ/BGEZ

Currently for testing bits above 14-th the following instructions emitted:

 LUI $t1, 0x1000         # 0x10000000
 AND $t0, $t1, $t0
 BEQ/BNE $t0, $Lxx

However there's shorter & faster alternative, just need to
shift the bit of interest to the sign bit and jump with BLTZ/BGEZ.
The code above can be replaced with:

 SLL $t0, $0, 3
 BGEZ/BLTZ $t0, $Lxx

Not sure if it can be applied to MIPS64 without EXT/INS instructions
and to older MIPS revisions (I..V).
But for MIPS32 it helps reduce code size by removing 1 insn per ~700.
evaluated on linux kernel and python3.11.=