From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 4E0083858C50; Tue, 12 Sep 2023 13:10:25 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 4E0083858C50 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1694524225; bh=xbQtun9H/9Fsw7+gliyMkh2LtCClVb66d5muAUms9nY=; h=From:To:Subject:Date:In-Reply-To:References:From; b=hPpDqz9CAxS1bOi5y0plbU+wczKtacPgd2cZ+oTJSilZEccob7G2h7XMSuY7bIB89 N/uPJ26bIkVbLXauC9GxQnCn6EpR85HGefIRcfGIWm69w/bBNt7ddgWyF8dz888GBm +wghENtYw83Z2J0xzgfngS6VlWrqn349gCJJXS1I= From: "lis8215 at gmail dot com" To: gcc-bugs@gcc.gnu.org Subject: [Bug rtl-optimization/111384] missed optimization: GCC adds extra any extend when storing subreg#0 multiple times Date: Tue, 12 Sep 2023 13:10:24 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: rtl-optimization X-Bugzilla-Version: 14.0 X-Bugzilla-Keywords: missed-optimization X-Bugzilla-Severity: normal X-Bugzilla-Who: lis8215 at gmail dot com X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D111384 --- Comment #2 from Siarhei Volkau --- Well what the godbolt says with -O2 -fomit-frame-pointer. ARM: uxth r0, r0 @ << zero extend strh r0, [r1] strh r0, [r2] bx lr ARM64: and w0, w0, 65535 @ << zero extend strh w0, [x1] strh w0, [x2] ret MIPS64: andi $4,$4,0xffff @ << zero extend sh $4,0($5) jr $31 sh $4,0($6) MRISC32: shuf r1, r1, #2888 @ << zero extend sth r1, [r2] sth r1, [r3] ret RISC-V: slli a0,a0,16 @ << zero extend srli a0,a0,16 @ << zero extend sh a0,0(a1) sh a0,0(a2) ret RISC-V (64-bit): slli a0,a0,48 @ << zero extend srli a0,a0,48 @ << zero extend sh a0,0(a1) sh a0,0(a2) ret Xtensa ESP32: entry sp, 32 extui a2, a2, 0, 16 @ << zero extend s16i a2, a3, 0 s16i a2, a4, 0 retw.n Loongarch64: bstrpick.w $r4,$r4,15,0 @ << zero extend st.h $r4,$r5,0 st.h $r4,$r6,0 jr $r1 MIPS: andi $4,$4,0xffff @ << zero extend sh $4,0($5) jr $31 sh $4,0($6) SH: extu.w r4,r4 @ << zero extend mov.w r4,@r5 rts=20=20=20=20=20 mov.w r4,@r6 Other available at godbolt (x86-64/Power/Power64/s390) unaffected.=