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From: "rdapp at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug middle-end/111401] Middle-end: Missed optimization of
 MASK_LEN_FOLD_LEFT_PLUS
Date: Wed, 13 Sep 2023 16:52:33 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D111401

Robin Dapp <rdapp at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |rdapp at gcc dot gnu.org

--- Comment #2 from Robin Dapp <rdapp at gcc dot gnu.org> ---
I played around with this a bit.  Emitting a COND_LEN in if-convert is easy:

_ifc__35 =3D .COND_ADD (_23, init_20, _8, init_20);

However, during reduction handling we rely on the reduction being a gimple
assign and binary operation, though so I needed to fix some places and indi=
ces
as well as the proper mask.

What complicates things a bit is that we assume that "init_20" (i.e. the
reduction def) occurs once when we have it twice in the COND_ADD.  I just
special cased that for now.  Is this the proper thing to do?

diff --git a/gcc/tree-vect-loop.cc b/gcc/tree-vect-loop.cc
index 23c6e8259e7..e99add3cf16 100644
--- a/gcc/tree-vect-loop.cc
+++ b/gcc/tree-vect-loop.cc
@@ -3672,7 +3672,7 @@ vect_analyze_loop (class loop *loop, vec_info_shared
*shared)
 static bool
 fold_left_reduction_fn (code_helper code, internal_fn *reduc_fn)
 {
-  if (code =3D=3D PLUS_EXPR)
+  if (code =3D=3D PLUS_EXPR || code =3D=3D IFN_COND_ADD)
     {
       *reduc_fn =3D IFN_FOLD_LEFT_PLUS;
       return true;
@@ -4106,8 +4106,11 @@ vect_is_simple_reduction (loop_vec_info loop_info,
stmt_vec_info phi_info,
           return NULL;
         }

-      nphi_def_loop_uses++;
-      phi_use_stmt =3D use_stmt;
+      if (use_stmt !=3D phi_use_stmt)
+       {
+         nphi_def_loop_uses++;
+         phi_use_stmt =3D use_stmt;
+       }

@@ -7440,6 +7457,9 @@ vectorizable_reduction (loop_vec_info loop_vinfo,
       if (i =3D=3D STMT_VINFO_REDUC_IDX (stmt_info))
        continue;

+      if (op.ops[i] =3D=3D op.ops[STMT_VINFO_REDUC_IDX (stmt_info)])
+       continue;
+

Apart from that I think what's mainly missing is making the added code nice=
r.=20
Going to attach a tentative patch later.=