[Bug target/111412] New: [release/gcc13 bug]RISC-V:ICE in phase 6 of vsetvl pass

["xuli1 at eswincomputing dot com" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111412

            Bug ID: 111412
           Summary: [release/gcc13 bug]RISC-V:ICE in phase 6 of vsetvl
                    pass
           Product: gcc
           Version: 13.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: xuli1 at eswincomputing dot com
  Target Milestone: ---

Created attachment 55899
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=55899&action=edit
testcase

Compile the code using -march=rv64gcv -mabi=lp64d -O2:
test:
        beq     a0,zero,.L2
        lui     a5,%hi(.LC0)
        flw     fa4,%lo(.LC0)(a5)
        fmv.s.x fa5,zero
        li      a3,1
        vfmv.v.f        v1,fa4 --> The vsetvl instruction was not set before 
                                   this,causing Illegal instruction (core 
                                   dumped)
.L5:
        slli    a5,a3,32
        srli    a5,a5,32
        vsetvli a5,a5,e32,m8,ta,mu
        beq     a5,zero,.L3
        mv      a4,a3
.....

Solution:
vsetvl pass has been refactored in gcc14, and the optimization process is more
reasonable than gcc13. This problem does not exist in gcc14.


Phase 6 of gcc13 is an optimization patch. Due to lack of consideration,
there will be some hidden bugs, so we decided to remove phase 6. 
Although the generated code will be redundant,the program is correct.