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From: "wilco at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/111416] [Armv7/v8 Mixing Bug]: 64-bit Sequentially
 Consistent Load can be Reordered before Store of RMW when v7 and v8
 Implementations are Mixed
Date: Tue, 31 Oct 2023 16:51:26 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D111416

Wilco <wilco at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           See Also|                            |https://gcc.gnu.org/bugzill
                   |                            |a/show_bug.cgi?id=3D111235

--- Comment #3 from Wilco <wilco at gcc dot gnu.org> ---
Fixed by commit r14-4365-g0731889c026bfe8d55c4851422ca5ec9d037f7a0=20

#include <stdatomic.h>
#include <stdint.h>

int64_t f (_Atomic int64_t *p)
{
  return atomic_load (p);
}

now generates with -O2 -mcpu=3Dcortex-a15:

        dmb     ish
        ldrd    r0, r1, [r0]
        dmb     ish
        bx      lr=