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From: "jeremy.bennett at embecosm dot com" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/111566] RISC-V Vector Fortran: ICE in final_scan_insn_1
 (final RTL pass)
Date: Tue, 03 Oct 2023 08:30:58 +0000
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X-Bugzilla-Keywords: ice-on-valid-code
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X-Bugzilla-Who: jeremy.bennett at embecosm dot com
X-Bugzilla-Status: RESOLVED
X-Bugzilla-Resolution: FIXED
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D111566

Jeremy Bennett <jeremy.bennett at embecosm dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         Resolution|---                         |FIXED
             Status|UNCONFIRMED                 |RESOLVED

--- Comment #7 from Jeremy Bennett <jeremy.bennett at embecosm dot com> ---
I can confirm this is resolved, and also that SPEC CPU 2017 627.cam4_s comp=
iles
successfully.

Thanks for the patch. Marking as resolved.=