[Bug middle-end/111566] New: RISC-V Vector Fortran: ICE in final_scan_insn_1 (final RTL pass)

[Bug middle-end/111566] New: RISC-V Vector Fortran: ICE in final_scan_insn_1 (final RTL pass)

[jeremy.bennett at embecosm dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111566

            Bug ID: 111566
           Summary: RISC-V Vector Fortran: ICE in final_scan_insn_1 (final
                    RTL pass)
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: middle-end
          Assignee: unassigned at gcc dot gnu.org
          Reporter: jeremy.bennett at embecosm dot com
  Target Milestone: ---

Created attachment 55979
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=55979&action=edit
Reproducer

Issue discovered with the SPEC CPU 2017 627.cam4_s benchmark. It appears to be
an interaction between RISC-V vector and the -fmax-stack-var-size parameter.

Reproducer (test.f90)

module a
  integer,parameter :: SHR_KIND_R8 = selected_real_kind(12)
end module a
module b
  use a,  c => shr_kind_r8
contains
  subroutine d(cg , km, i1, i2)
    real (c) ch(i2,km)
    real (c) cg(4,i1:i2,km)
    real  dc(i2,km)
    real(c) ci(i2,km)
    real(c) cj(i2,km)
    do k=2,ck
       do i=i1,0
          cl = ci(i,k) *ci(i,1) /      cj(i,k)+ch(i,1)
          cm = cg(1,i,k) - min(e,cg(1,i,co))
          dc(i,k) = sign(cm, cl)
       enddo
    enddo
    if ( cq == 0 ) then
       do i=i1,i2
          if( cr <=  cs ) then
             cg= sign( min(ct,   cg),  cg)
          endif
       enddo
    endif
  end subroutine d
end module b

Compile with:

riscv64-unknown-linux-gnu-gfortran -w -march=rv64gcv -mabi=lp64d -c     -Ofast
-ftree-vectorize --param=riscv-autovec-preference=scalable    
-fallow-argument-mismatch -fmax-stack-var-size=65536 test.f90

Output is:

   27 |   end subroutine d
      |                  ^
Error: could not split insn
(insn 967 168 1115 (set (mem/c:V16DI (plus:DI (reg/f:DI 2 sp)
                (const_int 128 [0x80])) [4 %sfp+[-1024, -16] S128 A128])
        (mem/c:V16DI (reg/f:DI 2 sp) [4 %sfp+[-1152, -16] S128 A128]))
"test.f90":16:44 1117 {*movv16di_mem_to_mem}
     (nil))
during RTL pass: final
test.f90:27:18: internal compiler error: in final_scan_insn_1, at final.cc:2808
0x9d3f63 _fatal_insn(char const*, rtx_def const*, char const*, int, char
const*)
        /home/jeremy/gittrees/mustang/gcc/gcc/rtl-error.cc:108
0x965949 final_scan_insn_1
        /home/jeremy/gittrees/mustang/gcc/gcc/final.cc:2808
0xe952af final_scan_insn(rtx_insn*, _IO_FILE*, int, int, int*)
        /home/jeremy/gittrees/mustang/gcc/gcc/final.cc:2887
0xe954f4 final_1
        /home/jeremy/gittrees/mustang/gcc/gcc/final.cc:1979
0xe9601a rest_of_handle_final
        /home/jeremy/gittrees/mustang/gcc/gcc/final.cc:4240
0xe9601a execute
        /home/jeremy/gittrees/mustang/gcc/gcc/final.cc:4318
Please submit a full bug report, with preprocessed source (by using
-freport-bug).
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.

System information
==================

Using built-in specs.
COLLECT_GCC=riscv64-unknown-linux-gnu-gfortran
COLLECT_LTO_WRAPPER=/home/jeremy/gittrees/mustang/install/libexec/gcc/riscv64-unknown-linux-gnu/14.0.0/lto-wrapper
Target: riscv64-unknown-linux-gnu
Configured with: /home/jeremy/gittrees/mustang/gcc/configure
--target=riscv64-unknown-linux-gnu
--prefix=/home/jeremy/gittrees/mustang/install
--with-sysroot=/home/jeremy/gittrees/mustang/install/sysroot
--with-pkgversion=g59d27cc55a0 --with-system-zlib --enable-shared --enable-tls
--enable-languages=c,c++,fortran --disable-libmudflap --disable-libssp
--disable-libquadmath --disable-libsanitizer --disable-nls --disable-bootstrap
--src=/home/jeremy/gittrees/mustang/gcc --enable-multilib --with-abi=lp64d
--with-arch=rv64gc --with-tune= --with-isa-spec=20191213 'CFLAGS_FOR_TARGET=-O2
   -mcmodel=medany' 'CXXFLAGS_FOR_TARGET=-O2    -mcmodel=medany'
Thread model: posix
Supported LTO compression algorithms: zlib
gcc version 14.0.0 20230923 (experimental) (g59d27cc55a0)

[Bug target/111566] RISC-V Vector Fortran: ICE in final_scan_insn_1 (final RTL pass)

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111566

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
          Component|middle-end                  |target
           Keywords|                            |ice-on-valid-code

--- Comment #1 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
fmax-stack-var-size just changes if (the VLA) dc, ch, ci, and cj are allocated
on the stack or in the heap.

[Bug target/111566] RISC-V Vector Fortran: ICE in final_scan_insn_1 (final RTL pass)

[amylaar at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111566

Jorn Wolfgang Rennecke <amylaar at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |amylaar at gcc dot gnu.org

--- Comment #2 from Jorn Wolfgang Rennecke <amylaar at gcc dot gnu.org> ---
This also causes trouble with my cpymem patch.

With the *movv8si_mem_to_mem pattern, ira.cc:combine_and_move_insns
will eagerly transform

(insn 1606 1603 1608 77 (set (reg/f:SI 1187)
        (plus:SI (reg/f:SI 65 frame)
            (const_int -1248 [0xfffffffffffffb20])))
"/home/amylaar/embecosm/fsf-cme3/gcc/gcc/testsuite/c-c++-common/torture/complex-sign-add.c":44:0
discrim 126 4 {*addsi3}
     (nil))

(insn 1608 1606 1609 77 (set (reg:V8SI 1189)
        (mem/u/c:V8SI (reg/f:SI 5064) [0  S32 A128]))
"/home/amylaar/embecosm/fsf-cme3/gcc/gcc/testsuite/c-c++-common/torture/complex-sign-add.c":44:0
discrim 126 1151 {*movv8si}
     (expr_list:REG_DEAD (reg/f:SI 5064)
        (expr_list:REG_EQUAL (mem/u/c:V8SI (const:SI (plus:SI (symbol_ref:SI
("*.LANCHOR0") [flags 0x182])
                        (const_int 64 [0x40]))) [0  S32 A128])
            (nil))))

(insn 1609 1608 12961 77 (set (mem/v/c:V8SI (reg/f:SI 1187) [1  S32 A128])
        (reg:V8SI 1189))
"/home/amylaar/embecosm/fsf-cme3/gcc/gcc/testsuite/c-c++-common/torture/complex-sign-add.c":44:0
discrim 126 1151 {*movv8si}
     (expr_list:REG_DEAD (reg:V8SI 1189)
        (expr_list:REG_DEAD (reg/f:SI 1187)
            (nil))))

into


(insn 1608 1603 16000 77 (set (reg:V8SI 1189)
        (mem/u/c:V8SI (reg/f:SI 5064) [0  S32 A128]))
"/home/amylaar/embecosm/fsf-cme3/gcc/gcc/testsuite/c-c++-common/torture/complex-sign-add.c":44:0
discrim 126 1151 {*movv8si}
     (expr_list:REG_EQUIV (mem/u/c:V8SI (const:SI (plus:SI (symbol_ref:SI
("*.LANCHOR0") [flags 0x182])
                    (const_int 64 [0x40]))) [0  S32 A128])
        (expr_list:REG_DEAD (reg/f:SI 5064)
            (nil))))

(insn 16000 1608 1609 77 (set (reg/f:SI 1187)
        (plus:SI (reg/f:SI 65 frame)
            (const_int -1248 [0xfffffffffffffb20])))
"/home/amylaar/embecosm/fsf-cme3/gcc/gcc/testsuite/c-c++-common/torture/complex-sign-add.c":44:0
discrim 126 4 {*addsi3}
     (expr_list:REG_EQUIV (plus:SI (reg/f:SI 65 frame)
            (const_int -1248 [0xfffffffffffffb20]))
        (nil)))

(insn 1609 16000 12961 77 (set (mem/v/c:V8SI (reg/f:SI 1187) [1  S32 A128])
        (mem/u/c:V8SI (reg/f:SI 5064) [0  S32 A128]))
"/home/amylaar/embecosm/fsf-cme3/gcc/gcc/testsuite/c-c++-common/torture/complex-sign-add.c":44:0
discrim 126 -1
     (expr_list:REG_DEAD (reg:V8SI 1189)
        (expr_list:REG_DEAD (reg/f:SI 1187)
            (nil))))

during compilation of check_add_long_double.

When a pattern with a mandatory split is recognized, you must make sure it can
be split.  If the pattern ceases to be valid at some point during the
compilation, you must make sure it can be split or otherwise transformed
before another attempt to recognize it is made.

[Bug target/111566] RISC-V Vector Fortran: ICE in final_scan_insn_1 (final RTL pass)

[amylaar at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111566

--- Comment #3 from Jorn Wolfgang Rennecke <amylaar at gcc dot gnu.org> ---
riscv-v.cc:legitimize_move has:

          if (MEM_P (dest) && !REG_P (src))
            src = force_reg (mode, src);

          return false;

since src is passed by value, this is pointless.  The caller still had src
as a MEM.

[Bug target/111566] RISC-V Vector Fortran: ICE in final_scan_insn_1 (final RTL pass)

[amylaar at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111566

--- Comment #4 from Jorn Wolfgang Rennecke <amylaar at gcc dot gnu.org> ---
Also, the GET_MODE_BITSIZE (<MODE>mode).to_constant () <= MAX_BITS_PER_WORD
in the *mov<mode>_mem_to_mem splitter can generate unaligned accesses, yet it
is not guarded by a check that the target supports them.

[Bug target/111566] RISC-V Vector Fortran: ICE in final_scan_insn_1 (final RTL pass)

[amylaar at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111566

--- Comment #5 from Jorn Wolfgang Rennecke <amylaar at gcc dot gnu.org> ---
I had a look at riscv_legitimize_move.  It doesn't seem to suffer from quite
the same problem as legitimize_move does, but it could if another problem was
fixed: riscv_legitimize_move changes the rtl it's passed.  That can lead to
trouble if this is shared rtl.

[Bug target/111566] RISC-V Vector Fortran: ICE in final_scan_insn_1 (final RTL pass)

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111566

--- Comment #6 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Joern Rennecke <amylaar@gcc.gnu.org>:

https://gcc.gnu.org/g:f416a3fdbee32ae12b055b8e3e4ee11c3df7c117

commit r14-4353-gf416a3fdbee32ae12b055b8e3e4ee11c3df7c117
Author: Joern Rennecke <joern.rennecke@embecosm.com>
Date:   Sun Oct 1 06:13:37 2023 +0100

    Make riscv_vector::legitimize_move adjust SRC in the caller.

    2023-09-29  Joern Rennecke  <joern.rennecke@embecosm.com>
                Juzhe-Zhong  <juzhe.zhong@rivai.ai>

            PR target/111566

    gcc/
            * config/riscv/riscv-protos.h (riscv_vector::legitimize_move):
            Change second parameter to rtx *.
            * config/riscv/riscv-v.cc (risv_vector::legitimize_move): Likewise.
            * config/riscv/vector.md: Changed callers of
            riscv_vector::legitimize_move.
            (*mov<mode>_mem_to_mem): Remove.

    gcc/testsuite/

            * gcc.target/riscv/rvv/autovec/vls/mov-1.c: Adapt test.
            * gcc.target/riscv/rvv/autovec/vls/mov-10.c: Ditto.
            * gcc.target/riscv/rvv/autovec/vls/mov-3.c: Ditto.
            * gcc.target/riscv/rvv/autovec/vls/mov-5.c: Ditto.
            * gcc.target/riscv/rvv/autovec/vls/mov-7.c: Ditto.
            * gcc.target/riscv/rvv/autovec/vls/mov-8.c: Ditto.
            * gcc.target/riscv/rvv/autovec/vls/mov-9.c: Ditto.1
            * gcc.target/riscv/rvv/autovec/vls/mov-2.c: Removed.
            * gcc.target/riscv/rvv/autovec/vls/mov-4.c: Removed.
            * gcc.target/riscv/rvv/autovec/vls/mov-6.c: Removed.
            * gcc.target/riscv/rvv/fortran/pr111566.f90: New test.

    Co-Authored-By: Juzhe-Zhong  <juzhe.zhong@rivai.ai>

[Bug target/111566] RISC-V Vector Fortran: ICE in final_scan_insn_1 (final RTL pass)

[jeremy.bennett at embecosm dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111566

Jeremy Bennett <jeremy.bennett at embecosm dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         Resolution|---                         |FIXED
             Status|UNCONFIRMED                 |RESOLVED

--- Comment #7 from Jeremy Bennett <jeremy.bennett at embecosm dot com> ---
I can confirm this is resolved, and also that SPEC CPU 2017 627.cam4_s compiles
successfully.

Thanks for the patch. Marking as resolved.