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From: "patrick at rivosinc dot com" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/111634] RISC-V vector: ICE RTL check: expected code 'reg', have 'lo_sum' in rhs_regno, at rtl.h:1934
Date: Sat, 07 Oct 2023 09:03:10 +0000 [thread overview]
Message-ID: <bug-111634-4-9JNJQepBAi@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-111634-4@http.gcc.gnu.org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111634
Patrick O'Neill <patrick at rivosinc dot com> changed:
What |Removed |Added
----------------------------------------------------------------------------
Resolution|--- |FIXED
Status|UNCONFIRMED |RESOLVED
--- Comment #3 from Patrick O'Neill <patrick at rivosinc dot com> ---
Confirmed to be fixed on r14-4443-ga809a556dc0.
Built and ran testsuite on rv32/64gcv glibc/newlib with --enable-checking=rtl.
They all built successfully and no tests fail due to rtl checking!
prev parent reply other threads:[~2023-10-07 9:03 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-28 18:59 [Bug target/111634] New: " patrick at rivosinc dot com
2023-09-28 19:01 ` [Bug target/111634] " patrick at rivosinc dot com
2023-10-07 4:57 ` cvs-commit at gcc dot gnu.org
2023-10-07 9:03 ` patrick at rivosinc dot com [this message]
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