From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <gcc-bugzilla@gcc.gnu.org>
Received: by sourceware.org (Postfix, from userid 48)
	id 2AC743857031; Sat,  7 Oct 2023 04:57:44 +0000 (GMT)
DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 2AC743857031
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org;
	s=default; t=1696654664;
	bh=FbxY4zSJoFQw8CeoDpgMAZvSxdKxRxxkMUpq/0W721Y=;
	h=From:To:Subject:Date:In-Reply-To:References:From;
	b=d3jZleAuIdolqTvSicqwWAB02KLnDUM7wbM5qrQV/DQoXCkAE6GutzgXrjIgvJqRj
	 qdC8MF+hyPjpJbUHWUNTZm/mSrPaW8rkgrcyltYC1XIe0oTO6kTvQd6/QcvUk5cWEh
	 A6V9n02W3wI5THwdfeSzcrwyHkG8QN650m+Fuppc=
From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/111634] RISC-V vector: ICE RTL check: expected code
 'reg', have 'lo_sum' in rhs_regno, at rtl.h:1934
Date: Sat, 07 Oct 2023 04:57:43 +0000
X-Bugzilla-Reason: CC
X-Bugzilla-Type: changed
X-Bugzilla-Watch-Reason: None
X-Bugzilla-Product: gcc
X-Bugzilla-Component: target
X-Bugzilla-Version: 14.0
X-Bugzilla-Keywords: ice-checking, ice-on-valid-code
X-Bugzilla-Severity: normal
X-Bugzilla-Who: cvs-commit at gcc dot gnu.org
X-Bugzilla-Status: UNCONFIRMED
X-Bugzilla-Resolution: 
X-Bugzilla-Priority: P3
X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org
X-Bugzilla-Target-Milestone: ---
X-Bugzilla-Flags: 
X-Bugzilla-Changed-Fields: 
Message-ID: <bug-111634-4-AHx70LnvyC@http.gcc.gnu.org/bugzilla/>
In-Reply-To: <bug-111634-4@http.gcc.gnu.org/bugzilla/>
References: <bug-111634-4@http.gcc.gnu.org/bugzilla/>
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable
X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/
Auto-Submitted: auto-generated
MIME-Version: 1.0
List-Id: <gcc-bugs.sourceware.org>

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D111634

--- Comment #2 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <panli@gcc.gnu.org>:

https://gcc.gnu.org/g:a809a556dc0792a34fca7b754ff96ea3ea7d1e7f

commit r14-4443-ga809a556dc0792a34fca7b754ff96ea3ea7d1e7f
Author: Pan Li <pan2.li@intel.com>
Date:   Sat Oct 7 12:39:14 2023 +0800

    RISC-V: Bugfix for legitimize address PR/111634

    Given we have RTL as below.

    (plus:DI (mult:DI (reg:DI 138 [ g.4_6 ])
                      (const_int 8 [0x8]))
             (lo_sum:DI (reg:DI 167)
                        (symbol_ref:DI ("f") [flags 0x86] <var_decl
0x7fa96ea1cc60 f>)
    ))

    When handling (plus (plus (mult (a) (mem_shadd_constant)) (fp)) (C)) ca=
se,
    the fp will be the lo_sum operand as above. We have assumption that the=
 fp
    is reg but actually not here. It will have ICE when building with option
    --enable-checking=3Drtl.

    This patch would like to fix it by adding the REG_P to ensure the opera=
nd
    is a register. The test case gcc/testsuite/gcc.dg/pr109417.c covered th=
is
    fix when build with --enable-checking=3Drtl.

            PR target/111634

    gcc/ChangeLog:

            * config/riscv/riscv.cc (riscv_legitimize_address): Ensure
            object is a REG before extracting its' REGNO.

    Signed-off-by: Pan Li <pan2.li@intel.com>=