[Bug debug/111680] New: DWARF information inconstant with the generated RISC-V Binary

[Bug debug/111680] New: DWARF information inconstant with the generated RISC-V Binary

[king.chung at manchester dot ac.uk]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111680

            Bug ID: 111680
           Summary: DWARF information inconstant with the generated RISC-V
                    Binary
           Product: gcc
           Version: 12.2.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: debug
          Assignee: unassigned at gcc dot gnu.org
          Reporter: king.chung at manchester dot ac.uk
  Target Milestone: ---

Created attachment 56041
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=56041&action=edit
Screen capture of the Binary and DWARF data.

The DWARF information presented is not matching with the RISC-V binary. On the
attached picture, the left-hand side is the generated binary, and on the
right-hand side is the DWARF information. On the left, we can see the order of
operation is SP Change -> Value Store -> SP Change. However, on the right is SP
Change -> SP Change -> Value Store. If I did not understand the DWARF standard
wrong, the calculation is based on the most recent CFA value, which, in this
case, just by using the DWARF data, the saved value cannot be recovered.

Some discussions have been started on the RISC-V gnu toolchain Repo:
https://github.com/riscv-collab/riscv-gnu-toolchain/issues/1336

[Bug target/111680] DWARF information inconsistent with the generated RISC-V Binary

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111680

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Target|                            |riscv64-linux-gnu
          Component|debug                       |target

--- Comment #1 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
        .cfi_startproc
        addi    sp,sp,-2032
        .cfi_def_cfa_offset 2032
        sd      s0,2024(sp)
        sd      s1,2016(sp)
        sd      s2,2008(sp)
        add     a5,a3,a2
        sb      zero,0(a5)
        addi    sp,sp,-48
        .cfi_def_cfa_offset 2080
        .cfi_offset 8, -8
        .cfi_offset 9, -16
        .cfi_offset 18, -24

[Bug target/111680] DWARF information inconsistent with the generated RISC-V Binary

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111680

--- Comment #2 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Created attachment 56043
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=56043&action=edit
testcase

`-g0 -O3 -Wall -Wno-unused-label   -fno-reorder-blocks -march=rv64imafd`

[Bug target/111680] DWARF information inconsistent with the generated RISC-V Binary

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111680

--- Comment #3 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Created attachment 56044
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=56044&action=edit
Preprocessed source

[Bug target/111680] DWARF information inconsistent with the generated RISC-V Binary

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111680

--- Comment #4 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
MIPS64 does:
```
        daddiu  $sp,$sp,-2080
        .cfi_def_cfa_offset 2080
        daddu   $2,$7,$6
        sd      $16,2056($sp)
        sd      $17,2064($sp)
        sb      $0,0($2)
        li      $2,1                        # 0x1
        .cfi_offset 16, -24
        .cfi_offset 17, -16

```

Oh I see, the issue riscv has more limited range for the add so it needs to
split it up.

Anyways I think the the unwind tables are valid either way really because
register 8 (s0) is not modifed until later on.

[Bug target/111680] DWARF information inconsistent with the generated RISC-V Binary

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111680

--- Comment #5 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
https://sourceware.org/binutils/docs/as/CFI-directives.html#g_t_002ecfi_005fdef_005fcfa_005foffset-offset


I think you are reading the dwarf standard incorrectly.
It is the second cfi_def_cfa_offset is absolute offset and not an incremental
offset.

[Bug target/111680] DWARF information inconsistent with the generated RISC-V Binary

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111680

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Last reconfirmed|                            |2023-10-03
     Ever confirmed|0                           |1
             Status|UNCONFIRMED                 |NEW

--- Comment #6 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Actually I take that back, it looks like the dwarf2 pass did do the wrong
values as I don't think it is expecting 2 increments to the sp ...

[Bug debug/111680] DWARF information inconsistent with the generated RISC-V Binary

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111680

--- Comment #7 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Note I think most other targets create the stack offset in a register and then
do the add to the sp rather than having 2 add to sp which might be the reason
why this has not been seen until now too ...

[Bug debug/111680] DWARF information inconsistent with the generated RISC-V Binary

[king.chung at manchester dot ac.uk]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111680

--- Comment #8 from King Lok Chung <king.chung at manchester dot ac.uk> ---
It also looks like to me that the compiler is trying to be smart and save one
register use by reusing the SP, resulting in two SP offsets. In reality, it
could have used a6 or a7 easily.

Or might be the SP value is similar to the pointer address, which the compiler
trying take advantage of? This is just pure guessing.

[Bug debug/111680] DWARF information inconsistent with the generated RISC-V Binary

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111680

--- Comment #9 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
(In reply to King Lok Chung from comment #8)
> It also looks like to me that the compiler is trying to be smart and save
> one register use by reusing the SP, resulting in two SP offsets. In reality,
> it could have used a6 or a7 easily.

Kinda of, the issue is `addi    sp,sp,` has a limit for its immediate for the
add (you can't just add -2080 to sp).
So the backend decides to 2 `addi` and that confuses the rest of the
middle-end.


Note other backends do is rather:
Create the immediate in a register and then does the add to the sp to get the
increment.
That is how MIPS, AARCH64, rs6000, etc. implement the big stack increments and
does not confuse the rest of the GCC.

Anyways this should be fixed either by changing the riscv backend or fixing the
dwarf2 pass to do the correct thing (or maybe both).