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From: "juzhe.zhong at rivai dot ai" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/111720] RISC-V: Ugly codegen in RVV
Date: Sat, 07 Oct 2023 22:38:33 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D111720

--- Comment #3 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
(In reply to Andrew Pinski from comment #2)
> I noticed there is an ABI difference here.
>=20
> GCC is returning via a store to a0:
>         vsm.v   v1,0(a0)
>=20
> While LLVM is returning via v0 .
>=20
> Which one is correct?

Both are correct. We have a experiment ABI doc.

GCC also support same ABI but need --param=3Driscv-vector-abi

Then GCC ASM:

fn:
        lui     a5,%hi(.LANCHOR0)
        addi    sp,sp,-32
        addi    a5,a5,%lo(.LANCHOR0)
        vsetivli        zero,4,e64,m2,ta,ma
        li      a4,32
        vle64.v v8,0(a5)
        vse64.v v8,0(sp)
        vsetvli zero,a4,e8,m1,ta,ma
        vle8.v  v0,0(sp)
        vand.vi v0,v0,1
        addi    sp,sp,32
        jr      ra

GCC also return via v0 with enabling ABI.


The root cause is unnecessary load/store:

        vle64.v v8,0(a5)
        vse64.v v8,0(sp)=