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From: "juzhe.zhong at rivai dot ai" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/111720] RISC-V: Ugly codegen in RVV
Date: Sat, 07 Oct 2023 22:47:22 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D111720

--- Comment #8 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
(In reply to Andrew Pinski from comment #6)
> I suspect if __riscv_vle8_v_u8m1 gets lowered into a load on the gimple
> level, it might just work ...
>=20
> But it gets expanded as:
> (insn 14 13 0 (set (reg/v:RVVM1QI 134 [ varrD.56526 ])
>         (if_then_else:RVVM1QI (unspec:RVVMF8BI [
>                     (const_vector:RVVMF8BI repeat [
>                             (const_int 1 [0x1])
>                         ])
>                     (reg:DI 145)
>                     (const_int 2 [0x2]) repeated x2
>                     (const_int 0 [0])
>                     (reg:SI 66 vl)
>                     (reg:SI 67 vtype)
>                 ] UNSPEC_VPREDICATE)
>             (mem:RVVM1QI (reg:DI 144) [0  S[16, 16] A8])
>             (unspec:RVVM1QI [
>                     (reg:SI 0 zero)
>                 ] UNSPEC_VUNDEF))) "/app/example.c":7:23 -1
>      (nil))
>=20
> That seems complex.

You mean the normal load MEM_REF in GCC ?

I don't think we can do that since this intrinsic is defined with mask, len,
else value,...etc.=