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From: "lehua.ding at rivai dot ai" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/111725] New: Missed one vsetvl
Date: Sun, 08 Oct 2023 08:06:46 +0000
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X-Bugzilla-Type: new
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X-Bugzilla-Product: gcc
X-Bugzilla-Component: target
X-Bugzilla-Version: 14.0
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X-Bugzilla-Severity: normal
X-Bugzilla-Who: lehua.ding at rivai dot ai
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X-Bugzilla-Priority: P3
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D111725

            Bug ID: 111725
           Summary: Missed one vsetvl
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: lehua.ding at rivai dot ai
  Target Milestone: ---

online: https://godbolt.org/z/br456cPs8
C Code (compiler option: -march=3Drv32gcv -mabi=3Dilp32d -S -fno-schedule-i=
nsns
-fno-schedule-insns2  -fno-tree-vectorize -frename-registers -O2):

#include "riscv_vector.h"

float f (int8_t * restrict in, int8_t * restrict out, int n, int m, unsigned
cond, size_t vl, float scalar)
{
  vbool64_t mask =3D *(vbool64_t*) (in + 1000000);

  for (size_t i =3D 0; i < n; i++)
    {
      vfloat32mf2_t v =3D __riscv_vle32_v_f32mf2 ((float *)(in + i + 200),
__riscv_vsetvlmax_e32mf2 ());
      __riscv_vse32_v_f32mf2 ((float *)(out + i + 200), v,
__riscv_vsetvlmax_e32mf2 ());

      vfloat32mf2_t v2 =3D __riscv_vle32_v_f32mf2_tumu (mask, v, (float *)(=
in + i
+ 300), __riscv_vsetvlmax_e32mf2 ());
      __riscv_vse32_v_f32mf2_m (mask, (float *)(out + i + 300), v2,
__riscv_vsetvlmax_e32mf2 ());
    }

  vfloat32m1_t v =3D *(vfloat32m1_t*)(in + 300000);
  for (size_t i =3D 0; i < n; i++)
    {
      v =3D __riscv_vfmv_s_f_f32m1_tu (v, (scalar + i), 3);
    }
  v =3D __riscv_vfadd_vv_f32m1 (v,v, 3);
  return __riscv_vfmv_f_s_f32m1_f32 (v);
}

Assembly Code:

f:
        li      a5,999424
        addi    t0,a5,576
        add     t1,a0,t0
        vsetvli a4,zero,e32,mf2,tu,mu
        vlm.v   v0,0(t1)
        beq     a2,zero,.L2
        addi    t5,a0,200
        addi    t6,a1,300
        addi    a6,a2,200
        add     t3,a0,a6
.L3:
        vle32.v v1,0(t5)
        addi    a3,t6,-100
        vse32.v v1,0(a3)
        addi    t4,t5,100
        vle32.v v1,0(t4),v0.t
        vse32.v v1,0(t6),v0.t
        addi    t5,t5,1
        addi    t6,t6,1
        bne     t5,t3,.L3
        li      a5,299008
        addi    t0,a5,992
        add     t1,a0,t0
        vl1re32.v       v2,0(t1)
        li      a4,0
.L6:
        fcvt.s.wu       fa5,a4
        fadd.s  ft0,fa5,fa0
        vfmv.s.f        v2,ft0
        addi    a4,a4,1
        bne     a4,a2,.L6
        vfadd.vv        v3,v2,v2 # Miss vsetivli zero,3,e32,m1,ta,ma
        vfmv.f.s        fa0,v3
        ret
.L2:
        li      t2,299008
        addi    a1,t2,992
        add     a0,a0,a1
        vl1re32.v       v2,0(a0)
        vsetivli        zero,3,e32,m1,ta,ma
        vfadd.vv        v3,v2,v2
        vfmv.f.s        fa0,v3
        ret=