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From: "pinskia at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org> To: gcc-bugs@gcc.gnu.org Subject: [Bug middle-end/111743] shifts in bit field accesses don't combine with other shifts Date: Mon, 09 Oct 2023 20:40:08 +0000 [thread overview] Message-ID: <bug-111743-4-54B9VDfu1z@http.gcc.gnu.org/bugzilla/> (raw) In-Reply-To: <bug-111743-4@http.gcc.gnu.org/bugzilla/> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111743 Andrew Pinski <pinskia at gcc dot gnu.org> changed: What |Removed |Added ---------------------------------------------------------------------------- Ever confirmed|0 |1 CC| |pinskia at gcc dot gnu.org Severity|normal |enhancement Last reconfirmed| |2023-10-09 Status|UNCONFIRMED |NEW --- Comment #3 from Andrew Pinski <pinskia at gcc dot gnu.org> --- RTL wise we have: Trying 6, 8 -> 9: 6: {r108:DI=r105:DI 0>>0x20;clobber flags:CC;} REG_UNUSED flags:CC 8: {r110:SI=r108:DI#0&0x3ff;clobber flags:CC;} REG_UNUSED flags:CC REG_DEAD r108:DI 9: {r111:SI=r110:SI<<0x14;clobber flags:CC;} REG_DEAD r110:SI REG_UNUSED flags:CC Failed to match this instruction: (parallel [ (set (reg:SI 111) (and:SI (ashift:SI (subreg:SI (zero_extract:DI (reg/v:DI 105 [ bf ]) (const_int 32 [0x20]) (const_int 32 [0x20])) 0) (const_int 20 [0x14])) (const_int 1072693248 [0x3ff00000]))) (clobber (reg:CC 17 flags)) ]) This should have been simplified. Anyways bitfields have issues even on the gimple level as they are not lowered until expand ...
next prev parent reply other threads:[~2023-10-09 20:40 UTC|newest] Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-10-09 18:57 [Bug middle-end/111743] New: " andi-gcc at firstfloor dot org 2023-10-09 19:09 ` [Bug middle-end/111743] " pinskia at gcc dot gnu.org 2023-10-09 19:19 ` andi-gcc at firstfloor dot org 2023-10-09 20:40 ` pinskia at gcc dot gnu.org [this message] 2023-10-09 20:46 ` pinskia at gcc dot gnu.org 2023-10-10 0:32 ` andi-gcc at firstfloor dot org 2023-10-10 0:40 ` pinskia at gcc dot gnu.org
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