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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/111745] [14 Regression] ICE: in extract_insn, at
 recog.cc:2791 (unrecognizable insn) with -ffloat-store -mavx512fp16
 -mavx512vl
Date: Wed, 11 Oct 2023 04:58:48 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D111745

--- Comment #2 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by hongtao Liu <liuhongt@gcc.gnu.org>:

https://gcc.gnu.org/g:4efe9085d087a8d94261e4c38dd2ba840f3419ac

commit r14-4549-g4efe9085d087a8d94261e4c38dd2ba840f3419ac
Author: liuhongt <hongtao.liu@intel.com>
Date:   Tue Oct 10 11:32:09 2023 +0800

    Refine predicate of operands[2] in divv4hf3 with register_operand.

    In the expander, it will emit below insn.

    rtx tmp =3D gen_rtx_VEC_CONCAT (V4SFmode, operands[2],
                            force_reg (V2SFmode, CONST1_RTX (V2SFmode)));

    but *vec_concat<mode> only allow register_operand.

    gcc/ChangeLog:

            PR target/111745
            * config/i386/mmx.md (divv4hf3): Refine predicate of
            operands[2] with register_operand.

    gcc/testsuite/ChangeLog:

            * gcc.target/i386/pr111745.c: New test.=