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From: "juzhe.zhong at rivai dot ai" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug c/111765] New: RISC-V: Faild to vectorize gen-vect-34.c
Date: Tue, 10 Oct 2023 22:38:40 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D111765

            Bug ID: 111765
           Summary: RISC-V: Faild to vectorize gen-vect-34.c
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: c
          Assignee: unassigned at gcc dot gnu.org
          Reporter: juzhe.zhong at rivai dot ai
  Target Milestone: ---

https://godbolt.org/z/17qYYKWPM

float summul(int n, float *arg1, float *arg2)
{=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=
=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=
=20
    int i;=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=
=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20
    float res1 =3D 1.0;
    for(i =3D 0; i < n; i++) {
      if(arg2[i])=20
        res1 *=3D arg1[i];
    }=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=
=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=
=20=20
    return res1;=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=
=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20
}

I found both ARM SVE and RVV failed to vectorize this case wheras X86 can
vectorize it with -mavx2.

It seems that we need some tricks on both SVE and RVV backend ?=