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From: "amonakov at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/111768] X86: -march=native does not support alder lake big.little cache infor correctly
Date: Thu, 12 Oct 2023 09:55:07 +0000 [thread overview]
Message-ID: <bug-111768-4-FIo0SYI9w1@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-111768-4@http.gcc.gnu.org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111768
--- Comment #9 from Alexander Monakov <amonakov at gcc dot gnu.org> ---
(In reply to Arsen Arsenović from comment #8)
> indeed (but I believe it did happen with Alder Lake already, by accident,
> with AVX512 on P-cores but not on E-cores).
AFAIK on those Alder Lake CPUs you could only get AVX-512 by disabling E-cores
in the BIOS, so you couldn't boot in a configuration when both E-cores are
available and AVX-512 on P-cores is available.
next prev parent reply other threads:[~2023-10-12 9:55 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-11 10:11 [Bug bootstrap/111768] New: Bootstrap failure with -march=native on Intel Alder Lake CPUs because of differing cache sizes sjames at gcc dot gnu.org
2023-10-11 10:11 ` [Bug bootstrap/111768] " sjames at gcc dot gnu.org
2023-10-11 13:02 ` [Bug target/111768] X86: -march=native does not support alder lake big.little cache infor correctly pinskia at gcc dot gnu.org
2023-10-11 13:26 ` rguenth at gcc dot gnu.org
2023-10-11 13:55 ` crazylht at gmail dot com
2023-10-11 14:13 ` amonakov at gcc dot gnu.org
2023-10-12 6:32 ` arsen at gcc dot gnu.org
2023-10-12 6:59 ` amonakov at gcc dot gnu.org
2023-10-12 9:45 ` arsen at gcc dot gnu.org
2023-10-12 9:55 ` amonakov at gcc dot gnu.org [this message]
2023-10-12 10:49 ` crazylht at gmail dot com
2023-10-12 11:25 ` amonakov at gcc dot gnu.org
2023-10-12 11:32 ` rguenth at gcc dot gnu.org
2023-10-12 13:23 ` stormbyte at gmail dot com
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