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From: "rguenth at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/111822] [12/13/14 Regression] during RTL pass:
 lr_shrinkage ICE: in operator[], at vec.h:910 with -O2 -m32
 -flive-range-shrinkage -fno-dce -fnon-call-exceptions since
 r12-5301-g045206450386bc
Date: Fri, 08 Mar 2024 13:28:46 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D111822

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |ebotcazou at gcc dot gnu.o=
rg

--- Comment #14 from Richard Biener <rguenth at gcc dot gnu.org> ---
(In reply to Uro=C5=A1 Bizjak from comment #13)
> (In reply to Richard Biener from comment #12)
>=20
> > > But I think, we could do better. Adding CC.
> >=20
> > We sure could, but I doubt it's too important?  Maybe for Go/Ada.
>=20
> Preloading stuff is simply loading from the same DImode address, so I'd
> think that EH_NOTE should be moved from the original insn to the new insn
> without much problems.
>=20
> Please note that on x86_32 split pass is later splitting DImode memory
> access to two SImode loads, this looks somehow harder problem as far as EH
> notes are concerned, as the one above.
>=20
> I'm not versed in this area, so I'll leave the fix to someone else.

On RTL I'd defer to Eric here.

Note for the correctness issue on branches I'd probably prefer the
"simple" approach (unless a true solution turns out equally simple).=