From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <gcc-bugzilla@gcc.gnu.org>
Received: by sourceware.org (Postfix, from userid 48)
	id 81E863858C01; Thu, 26 Oct 2023 07:08:17 +0000 (GMT)
DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 81E863858C01
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org;
	s=default; t=1698304097;
	bh=enPQPDLiNX4qrciEyGymvKXoGa1mzObt1ipmUqZCgyo=;
	h=From:To:Subject:Date:In-Reply-To:References:From;
	b=BJcXMF9+L4NfAWDT7XccMGK2P00jYtaRjfNAQZFj3c91Afa9cuSrRBwcRuw6S3VyI
	 2f1Hw4R+xCvfu1ygJGiWQwKSU7306DTm0A0cuqEvaOBxFFx13eDYHUmorQPctzxSoO
	 m7f0j2GeHX3+Gx4Ah2Y9xFlAEmij3t12MPhwyTyA=
From: "juzhe.zhong at rivai dot ai" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/112092] RISC-V: Wrong RVV code produced for vsetvl-11.c
 and vsetvlmax-8.c
Date: Thu, 26 Oct 2023 07:08:16 +0000
X-Bugzilla-Reason: CC
X-Bugzilla-Type: changed
X-Bugzilla-Watch-Reason: None
X-Bugzilla-Product: gcc
X-Bugzilla-Component: target
X-Bugzilla-Version: 14.0
X-Bugzilla-Keywords: wrong-code
X-Bugzilla-Severity: normal
X-Bugzilla-Who: juzhe.zhong at rivai dot ai
X-Bugzilla-Status: UNCONFIRMED
X-Bugzilla-Resolution: 
X-Bugzilla-Priority: P3
X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org
X-Bugzilla-Target-Milestone: ---
X-Bugzilla-Flags: 
X-Bugzilla-Changed-Fields: 
Message-ID: <bug-112092-4-hbG6dZsMWC@http.gcc.gnu.org/bugzilla/>
In-Reply-To: <bug-112092-4@http.gcc.gnu.org/bugzilla/>
References: <bug-112092-4@http.gcc.gnu.org/bugzilla/>
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable
X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/
Auto-Submitted: auto-generated
MIME-Version: 1.0
List-Id: <gcc-bugs.sourceware.org>

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D112092

--- Comment #6 from JuzheZhong <juzhe.zhong at rivai dot ai> ---

> I have troubles chasing one down and the source code is so
> convoluted with macros I can't even find the implementation.

I am sorry for causing confusion to you here.

But because of the RVV fusion rules are so complicated, we define it in

riscv-vsetvl.def. To understand the codes, I suggest you directly read the
riscv-vsetvl.def

We define all compatible, fusion, available rules there.

For example, vle16.v (e16, m1 ) is compatible with vadd.vv (e32, mf2 ),
In this case, adjacent 2 instructions "vle16" (e16m1) and vadd.vv (e32mf2) =
can
have the same vsetvl (vsetvl e32mf2).

Wheras vsub.vv(e16,m1) and vadd (e32 mf2), they are not compatible.=