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From: "juzhe.zhong at rivai dot ai" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/112092] RISC-V: Wrong RVV code produced for vsetvl-11.c
 and vsetvlmax-8.c
Date: Thu, 26 Oct 2023 01:46:46 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D112092

JuzheZhong <juzhe.zhong at rivai dot ai> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |juzhe.zhong at rivai dot ai

--- Comment #1 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
No, it is correct. It's the fancy optimization we have done in VSETVL PASS.

e16mf2 is same ratio e32m1.

The later loop demand e32m1 and TU, so we fuse it into e16mf2
(__riscv_vsetvl_e16mf2(avl)), change it into e32m1 and TU.

This is a valid optimization.

You can change e16mf2 into e16m1. I am sure the fusion will be blocked.=