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From: "pinskia at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug middle-end/112098] suboptimal optimization of inverted bit
 extraction
Date: Thu, 26 Oct 2023 20:07:16 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D112098

--- Comment #3 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Trying 6, 7, 8 -> 9:
    6: {r105:SI=3Dr108:SI 0>>0x9;clobber flags:CC;}
      REG_DEAD r108:SI
      REG_UNUSED flags:CC
    7: {r106:SI=3Dr105:SI&0x1;clobber flags:CC;}
      REG_DEAD r105:SI
      REG_UNUSED flags:CC
    8: {r107:SI=3Dr106:SI^0x1;clobber flags:CC;}
      REG_DEAD r106:SI
      REG_UNUSED flags:CC
    9: {r103:SI=3Dr107:SI<<0x4;clobber flags:CC;}
      REG_DEAD r107:SI
      REG_UNUSED flags:CC
Failed to match this instruction:
(parallel [
        (set (reg:SI 103)
            (and:SI (lshiftrt:SI (xor:SI (reg:SI 108)
                        (const_int 512 [0x200]))
                    (const_int 5 [0x5]))
                (const_int 16 [0x10])))
        (clobber (reg:CC 17 flags))
    ])


The xor here maybe should have been not. But I can't remember if we allow 4=
->3
combining or just 4->2.=