[Bug c/112102] New: Inefficient Integer multiplication on MIPS processors

[Bug c/112102] New: Inefficient Integer multiplication on MIPS processors

[kazeemanuar at googlemail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112102

            Bug ID: 112102
           Summary: Inefficient Integer multiplication on MIPS processors
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: c
          Assignee: unassigned at gcc dot gnu.org
          Reporter: kazeemanuar at googlemail dot com
  Target Milestone: ---

Running integer multiplication with the -Os flag enabled can generate 2
unnecessary NOP instructions. This increases the cost of integer multiplication
from 7 to 9 cycles in most cases.


Example code:
int test(int a, int b, int c, int d)
{
     return 788*a + 789 * b + 187 + c + d;
}

output:
        li      $2,788
        mult    $4,$2
        li      $2,789  <--- could be moved down into one of the NOPs
        mflo    $4
        nop
        nop
        mult    $5,$2
        mflo    $5
        addu    $4,$4,$5
        addiu   $4,$4,187 <--- could be moved up into one of the NOPs
        addu    $4,$4,$6  <--- could be moved up into one of the NOPs
        jr      $31
        addu    $2,$4,$7

This happens on all GCC versions as far as I can tell.
Compiler explorer link: https://godbolt.org/z/M3x3s3KhM

[Bug c/112102] Inefficient Integer multiplication on MIPS processors

[kazeemanuar at googlemail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112102

--- Comment #1 from Kaze Emanuar <kazeemanuar at googlemail dot com> ---
Ignore the line about cycle counts. That was only applicable to my use case
before I realized GCC does this for all MIPS architectures. Sorry!

[Bug target/112102] Inefficient Integer multiplication on MIPS processors

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112102

--- Comment #2 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
-march=mips32r2 removes the nops. Iirc there was a hazard between the mflo and
mult instructions for older architectures.

[Bug target/112102] Inefficient Integer multiplication on MIPS processors

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112102

--- Comment #3 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Which mips arch are you really trying to compile for?
Mips 1, 2, 4 or mips32 (r1-r5 or r6).
There are many different ones and mips32 (and above) does not have any delay
slots/hazards for the mult instruction.

[Bug target/112102] Inefficient Integer multiplication on MIPS processors

[kazeemanuar at googlemail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112102

--- Comment #4 from Kaze Emanuar <kazeemanuar at googlemail dot com> ---
I'm using the vr4300 (Nintendo 64). It does have the hazard between mult and
mflos. MULT can't be within 2 instructions of the MFLO. This shouldn't be an
issue here though since there were 3 instructions available to put into the 2
NOP slots the MULT<>MFLO clash caused.

[Bug target/112102] Inefficient Integer multiplication on MIPS processors

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112102

--- Comment #5 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
/* True if mflo and mfhi can be immediately followed by instructions
   which write to the HI and LO registers.

   According to MIPS specifications, MIPS ISAs I, II, and III need
   (at least) two instructions between the reads of HI/LO and
   instructions which write them, and later ISAs do not.  Contradicting
   the MIPS specifications, some MIPS IV processor user manuals (e.g.
   the UM for the NEC Vr5000) document needing the instructions between
   HI/LO reads and writes, as well.  Therefore, we declare only MIPS32,
   MIPS64 and later ISAs to have the interlocks, plus any specific
   earlier-ISA CPUs for which CPU documentation declares that the
   instructions are really interlocked.  */
#define ISA_HAS_HILO_INTERLOCKS (mips_isa_rev >= 1                      \
                                 || TARGET_MIPS5500                     \
                                 || TARGET_MIPS5900                     \
                                 || TARGET_LOONGSON_2EF)


So the question becomes what are you compiling for?

[Bug target/112102] Inefficient Integer multiplication on MIPS processors

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112102

--- Comment #6 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
It just happened the scheduler didn't schedule it that way. Scheduling is NP
complete problem too.

[Bug target/112102] Inefficient Integer multiplication on MIPS processors

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112102

--- Comment #7 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Also is this function from real code or just an example to show the issue?
I suspect in real code you either have 2 extra nops or a scheduling bubble. the
nops might not make a huge difference ...

[Bug target/112102] Inefficient Integer multiplication on MIPS processors

[kazeemanuar at googlemail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112102

--- Comment #8 from Kaze Emanuar <kazeemanuar at googlemail dot com> ---
This code is just an example, but I have seen this issue appear in many of my
collision functions. I agree it's not a huge issue in my use case, but it'd
still be cool to have this work well. I can work around it with inline assembly
if this is not deemed an important enough issue to address.