From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <gcc-bugzilla@gcc.gnu.org>
Received: by sourceware.org (Postfix, from userid 48)
	id 338833858285; Mon, 11 Dec 2023 07:56:37 +0000 (GMT)
DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 338833858285
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org;
	s=default; t=1702281397;
	bh=SVEzGaZy6uwgJg9ENIV8hAqXH3L79iV863WOXbU7olk=;
	h=From:To:Subject:Date:In-Reply-To:References:From;
	b=rMDSm6FuKecDhW2UuFWEhvQI513UWSNAA4/6s/wzCXPpufNznexCP/9At0QsYLC2A
	 vsmf2hOOyz5L1pP2iKklMX17/iaYTVCo+ZtFXyp2aPhGKYwIzqldZo8PVyCs3PB6kK
	 BGEYiwnScMXjZFIKj/vWKHtMJQUQD3ouwitswQcY=
From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/112431] RISC-V GCC-15 feature: Support register overlap
 on widen RVV instructions
Date: Mon, 11 Dec 2023 07:56:35 +0000
X-Bugzilla-Reason: CC
X-Bugzilla-Type: changed
X-Bugzilla-Watch-Reason: None
X-Bugzilla-Product: gcc
X-Bugzilla-Component: target
X-Bugzilla-Version: 14.0
X-Bugzilla-Keywords: missed-optimization
X-Bugzilla-Severity: enhancement
X-Bugzilla-Who: cvs-commit at gcc dot gnu.org
X-Bugzilla-Status: UNCONFIRMED
X-Bugzilla-Resolution: 
X-Bugzilla-Priority: P3
X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org
X-Bugzilla-Target-Milestone: ---
X-Bugzilla-Flags: 
X-Bugzilla-Changed-Fields: 
Message-ID: <bug-112431-4-Zbm8Rt63Qx@http.gcc.gnu.org/bugzilla/>
In-Reply-To: <bug-112431-4@http.gcc.gnu.org/bugzilla/>
References: <bug-112431-4@http.gcc.gnu.org/bugzilla/>
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable
X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/
Auto-Submitted: auto-generated
MIME-Version: 1.0
List-Id: <gcc-bugs.sourceware.org>

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D112431

--- Comment #15 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <panli@gcc.gnu.org>:

https://gcc.gnu.org/g:7e854b58084c131fceca9e8fa9dcc7469972e69d

commit r14-6400-g7e854b58084c131fceca9e8fa9dcc7469972e69d
Author: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date:   Sat Dec 9 12:06:29 2023 +0800

    RISC-V: Support highest overlap for wv instructions

    According to RVV ISA, we can allow vwadd.wv v2, v2, v3 overlap.

    Before this patch:

            nop
            vsetivli        zero,4,e8,m4,tu,ma
            vle16.v v8,0(a0)
            vmv8r.v v0,v8
            vwsub.wv        v0,v8,v12
            nop
            addi    a4,a0,100
            vle16.v v8,0(a4)
            vmv8r.v v24,v8
            vwsub.wv        v24,v8,v12
            nop
            addi    a4,a0,200
            vle16.v v8,0(a4)
            vmv8r.v v16,v8
            vwsub.wv        v16,v8,v12
            nop

    After this patch:

            nop
            vsetivli        zero,4,e8,m4,tu,ma
            vle16.v v0,0(a0)
            vwsub.wv        v0,v0,v4
            nop
            addi    a4,a0,100
            vle16.v v24,0(a4)
            vwsub.wv        v24,v24,v28
            nop
            addi    a4,a0,200
            vle16.v v16,0(a4)
            vwsub.wv        v16,v16,v20

            PR target/112431

    gcc/ChangeLog:

            * config/riscv/vector.md: Support highest overlap for wv
instructions.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/base/pr112431-39.c: New test.
            * gcc.target/riscv/rvv/base/pr112431-40.c: New test.
            * gcc.target/riscv/rvv/base/pr112431-41.c: New test.=