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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/112431] RISC-V GCC-15 feature: Support register overlap
 on widen RVV instructions
Date: Thu, 30 Nov 2023 02:40:02 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D112431

--- Comment #6 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The trunk branch has been updated by Lehua Ding <lhtin@gcc.gnu.org>:

https://gcc.gnu.org/g:8614cbb253484e28c3eb20cde4d1067aad56de58

commit r14-5984-g8614cbb253484e28c3eb20cde4d1067aad56de58
Author: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date:   Thu Nov 30 10:36:30 2023 +0800

    RISC-V: Support highpart overlap for floating-point widen instructions

    This patch leverages the approach of vwcvt/vext.vf2 which has been
approved.
    Their approaches are totally the same.

    Tested no regression and committed.

            PR target/112431

    gcc/ChangeLog:

            * config/riscv/vector.md: Add widenning overlap.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/base/pr112431-10.c: New test.
            * gcc.target/riscv/rvv/base/pr112431-11.c: New test.
            * gcc.target/riscv/rvv/base/pr112431-12.c: New test.
            * gcc.target/riscv/rvv/base/pr112431-13.c: New test.
            * gcc.target/riscv/rvv/base/pr112431-14.c: New test.
            * gcc.target/riscv/rvv/base/pr112431-15.c: New test.
            * gcc.target/riscv/rvv/base/pr112431-7.c: New test.
            * gcc.target/riscv/rvv/base/pr112431-8.c: New test.
            * gcc.target/riscv/rvv/base/pr112431-9.c: New test.=