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From: "kito at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug c/112431] RISC-V GCC-15 feature: Support register overlap on
 widen RVV instructions
Date: Wed, 08 Nov 2023 01:56:19 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D112431

--- Comment #3 from Kito Cheng <kito at gcc dot gnu.org> ---
Share some thought from my end: we've tried at least 3 different approach on
LLVM side before, and now we model that as "partial early clobber", we plan=
 to
upstream  this on LLVM side but just didn't get high enough priority yet :(

What means? Give some practical example to demo the idea:

1. It's normal live range without early clobber

vadd x, y z # y and z is dead after this use.

|---------------------|
| read  |     y    z  |
| write | x           |
|---------------------|


2. It's live range with early clobber.

vadd x, y z # y and z is dead after this use, and assume x is early clobber.

|---------------------|
| read  | x   y    z  |
| write | x           |
|---------------------|


3. It's live range with partial early clobber.

vwadd.vv x, y, z # x is two time larger than y and z

So we split x into xh and xl to represent the high part and low part, and
assume  high part can be overlap with others.

|------------------------|
| read  |    xl  y    z  |
| write | xh xl          |
|------------------------|

And following case is assume high part can overlap with others:

|------------------------|
| read  | xh     y    z  |
| write | xh xl          |
|------------------------|

Then the register allocator should able to did the overlapping allocation
naturally IF we build live range.=