From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 9AB573858D3C; Wed, 8 Nov 2023 01:47:20 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 9AB573858D3C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1699408040; bh=OybVcn5MjMBv35ykHT5/7aq4o6CHgLEorjoUHtVE2Ho=; h=From:To:Subject:Date:In-Reply-To:References:From; b=AKdeB7Wfmr0qyXU6sNuMZXsP+ECXsf1ilP0cByPY5nkL3+Srav1gIbD2hh6Ib1wsh ONObSgr5XyARvVyPKEkPNWgGo6UTBgp+TPa3QO9DGsIBgHG8L4pDgfbUcxySE6w/nj eKmIy9eCQy5Kqkp2TsN6Md5eIsf8cIA/TFEWD7cY= From: "juzhe.zhong at rivai dot ai" To: gcc-bugs@gcc.gnu.org Subject: [Bug c/112433] RISC-V GCC-15 feature: Split register allocation into RVV and non-RVV, and make vsetvl PASS run between them Date: Wed, 08 Nov 2023 01:47:20 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: c X-Bugzilla-Version: 14.0 X-Bugzilla-Keywords: X-Bugzilla-Severity: normal X-Bugzilla-Who: juzhe.zhong at rivai dot ai X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D112433 --- Comment #2 from JuzheZhong --- (In reply to Kito Cheng from comment #1) > Give few more background why LLVM must do that way: LLVM can't allocate n= ew > pseudo register during register allocation process, however spilling vect= or > register with specific length may require scratch register to setting the= VL. >=20 > And the benefit of more exactly live range for GPR is kind of by-products > which we didn't aware during the discussion stage :P Yes. I was aware of this long time ago that's why our internal rewrite VSET= VL PASS is still running before RA.=