[Bug c/112433] New: RISC-V GCC-15 feature: Split register allocation into RVV and non-RVV, and make vsetvl PASS run between them

[Bug c/112433] New: RISC-V GCC-15 feature: Split register allocation into RVV and non-RVV, and make vsetvl PASS run between them

[juzhe.zhong at rivai dot ai]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112433

            Bug ID: 112433
           Summary: RISC-V GCC-15 feature: Split register allocation into
                    RVV and non-RVV, and make vsetvl PASS run between them
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: c
          Assignee: unassigned at gcc dot gnu.org
          Reporter: juzhe.zhong at rivai dot ai
  Target Milestone: ---

It's inspired by recent LLVM patch:
https://github.com/llvm/llvm-project/pull/70549

Consider this following situation (before RA):

p1: def r136
p2: vadd.vv (use r136)
p3: vadd.vv (use r136)

note r136 is AVL.

We currently run VSETVL PASS after RA which makes r136 register live range
from p1 to p3.

However, if we are able to split RVV and non-RVV register allocation as
follows:

PASS 1: allocate only RVV registers.
PASS 2: VSETVL PASS.
PASS 3: allocate all non-RVV registers.

Then after VSETVL PASS, we will end up with:

p1: def r136
p2: vsetvl zero, r136
p3: vadd.vv (use none)
p4: vadd.vv (use none)

Then r136 live range will be shorten from p1 to p2.

It should be easily addressed since RVV is different REG_CLASS.

This feature is going to be supported by Lehua in GCC-15.

[Bug c/112433] RISC-V GCC-15 feature: Split register allocation into RVV and non-RVV, and make vsetvl PASS run between them

[kito at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112433

--- Comment #1 from Kito Cheng <kito at gcc dot gnu.org> ---
Give few more background why LLVM must do that way: LLVM can't allocate new
pseudo register during register allocation process, however spilling vector
register with specific length may require scratch register to setting the VL.

And the benefit of more exactly live range for GPR is kind of by-products which
we didn't aware during the discussion stage :P

[Bug c/112433] RISC-V GCC-15 feature: Split register allocation into RVV and non-RVV, and make vsetvl PASS run between them

[juzhe.zhong at rivai dot ai]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112433

--- Comment #2 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
(In reply to Kito Cheng from comment #1)
> Give few more background why LLVM must do that way: LLVM can't allocate new
> pseudo register during register allocation process, however spilling vector
> register with specific length may require scratch register to setting the VL.
> 
> And the benefit of more exactly live range for GPR is kind of by-products
> which we didn't aware during the discussion stage :P

Yes. I was aware of this long time ago that's why our internal rewrite VSETVL
PASS
is still running before RA.

[Bug target/112433] RISC-V GCC-15 feature: Split register allocation into RVV and non-RVV, and make vsetvl PASS run between them

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112433

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Severity|normal                      |enhancement

[Bug target/112433] RISC-V GCC-15 feature: Split register allocation into RVV and non-RVV, and make vsetvl PASS run between them

[juzhe.zhong at rivai dot ai]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112433

--- Comment #3 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
Just talked with Lehua offline.

We don't think splitting RA can improve performance a lot.
We should consider it more seriously instead of support this blindly.
Since splitting RA will increase compile-time significantly with running RA
twice (RA consume most of the compile-time).

[Bug target/112433] RISC-V GCC-15 feature: Split register allocation into RVV and non-RVV, and make vsetvl PASS run between them

[kito at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112433

--- Comment #4 from Kito Cheng <kito at gcc dot gnu.org> ---
Yeah, 3 major goal in LLVM is improving scheduling, partial spilling and
re-materialization, but none of those points are issue for RISC-V GCC :P

Ref:
https://docs.google.com/presentation/d/1BOYNYKe1T-u3Q5HXRrcObLUkdKSPASmnuQTkALvJXto/edit