[Bug target/112445] [14 Regression] ICE: in lra_split_hard_reg_for, at lra-assigns.cc:1861 unable to find a register to spill: {*umulditi3_1} with -O -march=cascadelake -fwrapv since r14-4968-g89e5d902fc55ad

["jakub at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112445

Jakub Jelinek <jakub at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |jakub at gcc dot gnu.org,
                   |                            |segher at gcc dot gnu.org,
                   |                            |uros at gcc dot gnu.org,
                   |                            |vmakarov at gcc dot gnu.org

--- Comment #4 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
I think this goes wrong during combine.
Before combine, we have:
(insn 8 7 10 2 (set (subreg:HI (reg:QI 152) 0)
        (zero_extract:HI (reg:HI 1 dx [ cu8_0 ])
            (const_int 8 [0x8])
            (const_int 8 [0x8]))) "pr112445.c":11:1 114 {*extzvhi}
     (expr_list:REG_DEAD (reg:HI 1 dx [ cu8_0 ])
        (nil)))
...
tons of insns including
(insn 36 34 37 2 (parallel [
            (set (reg:TI 142 [ _66 ])
                (mult:TI (zero_extend:TI (reg:DI 171 [ cu8_0 ]))
                    (zero_extend:TI (subreg:DI (reg:TI 104 [ _10 ]) 0))))
            (clobber (reg:CC 17 flags))
        ]) "pr112445.c":12:9 522 {*umulditi3_1}
     (expr_list:REG_DEAD (reg:DI 171 [ cu8_0 ])
        (expr_list:REG_UNUSED (reg:CC 17 flags)
            (nil))))
...
(insn 41 38 44 2 (set (reg:DI 177 [ cu8_0+1 ])
        (zero_extend:DI (reg:QI 152))) "pr112445.c":12:9 170 {zero_extendqidi2}
     (expr_list:REG_DEAD (reg:QI 152)
        (nil)))
and combine merges insn 41 with insn 8 across 20 other insns:
Trying 8 -> 41:
    8: r152:QI#0=zero_extract(dx:HI,0x8,0x8)
      REG_DEAD dx:HI
   41: r177:DI=zero_extend(r152:QI)
      REG_DEAD r152:QI
Successfully matched this instruction:
(set (reg:DI 177 [ cu8_0+1 ])
    (zero_extract:DI (reg:DI 1 dx [ cu8_0 ])
        (const_int 8 [0x8])
        (const_int 8 [0x8])))
into:
(insn 41 38 44 2 (set (reg:DI 177 [ cu8_0+1 ])
        (zero_extract:DI (reg:DI 1 dx [ cu8_0 ])
            (const_int 8 [0x8])
            (const_int 8 [0x8]))) "pr112445.c":12:9 116 {*extzvdi}
     (expr_list:REG_DEAD (reg:HI 1 dx [ cu8_0 ])
        (nil)))
and by that it significantly extends the live range of rdx register, which is a
single class register.  Now insn 36 has constraints =r,A on output and %d,a on
first input and rm,rm on second input, meaning that it either has %rdx:%rax
destination (second alternative), or %rdx as one of the inputs, so when %rdx is
live across it, it can't be reloaded.
On that insn, the commit changed
-           (match_operand:DWIH 1 "nonimmediate_operand" "%d,0"))
+           (match_operand:DWIH 1 "register_operand" "%d,a"))
on the constraints, is that something that LRA used to handle fine (how?)?
Actually, in the r14-4967 reload dump I see:
(insn 223 193 202 2 (set (mem/c:DI (plus:DI (reg/f:DI 7 sp)
                (const_int 40 [0x28])) [3 %sfp+-40 S8 A64])
        (reg:DI 1 dx)) "pr112445.c":12:9 90 {*movdi_internal}
     (nil))
(insn 202 223 36 2 (set (reg:DI 0 ax [orig:142 _66 ] [142])
        (mem/c:DI (reg/f:DI 7 sp) [3 %sfp+-80 S8 A128])) "pr112445.c":12:9 90
{*movdi_internal}
     (nil))
(insn 36 202 203 2 (parallel [
            (set (reg:TI 0 ax [orig:142 _66 ] [142])
                (mult:TI (zero_extend:TI (reg:DI 0 ax [orig:142 _66 ] [142]))
                    (zero_extend:TI (reg:DI 37 r9 [orig:104 _10 ] [104]))))
            (clobber (reg:CC 17 flags))
        ]) "pr112445.c":12:9 522 {*umulditi3_1}
     (nil))
(insn 203 36 224 2 (set (mem/c:TI (reg/f:DI 7 sp) [3 %sfp+-80 S16 A128])
        (reg:TI 0 ax [orig:142 _66 ] [142])) "pr112445.c":12:9 89
{*movti_internal}
     (nil))
(insn 224 203 158 2 (set (reg:DI 1 dx)
        (mem/c:DI (plus:DI (reg/f:DI 7 sp)
                (const_int 40 [0x28])) [3 %sfp+-40 S8 A64])) "pr112445.c":12:9
90 {*movdi_internal}
     (nil))
so presumably LRA managed in that case to save and restore %rdx around it.
Is the problem the 0->a change when operand 0 is A?