[Bug tree-optimization/112450] RVV vectorization ICE in vect_get_loop_mask, at tree-vect-loop.cc:11037

["rguenth at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112450

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |rguenth at gcc dot gnu.org
             Target|                            |riscv

--- Comment #4 from Richard Biener <rguenth at gcc dot gnu.org> ---
(In reply to JuzheZhong from comment #1)
> Oh. I see we have cond_xxx pattern for VLS modes.
> 
> like V64HImdoe. But we don't support partial vectorization for VLS modes.
> 
> VLS modes are supposed to used as SIMD GNU vectorization.
> 
> As long as COND_XXX is enabled, loop vectorizer considers target support
> partial
> vectorization with mask and since no while_ult, then go through AVX512
> partial vectorization.

I think the bug is in the AVX512 code where it probably lacks some guards.
But in theory even with RVV you can do mask based vectorization of
partial loops, the AVX512 code doesn't require .WHILE_ULT but instead
uses regular compares.

I don't think you should work around this by disabling RVV patterns here.

I can have a look later what happens.

> It seems that for conditional operations, I should use backend RTL PASS to
> walk around that.