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From: "juzhe.zhong at rivai dot ai" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug tree-optimization/112450] RVV vectorization ICE in
 vect_get_loop_mask, at tree-vect-loop.cc:11037
Date: Thu, 09 Nov 2023 03:04:18 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D112450

--- Comment #1 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
Oh. I see we have cond_xxx pattern for VLS modes.

like V64HImdoe. But we don't support partial vectorization for VLS modes.

VLS modes are supposed to used as SIMD GNU vectorization.

As long as COND_XXX is enabled, loop vectorizer considers target support
partial
vectorization with mask and since no while_ult, then go through AVX512 part=
ial
vectorization.

It seems that for conditional operations, I should use backend RTL PASS to =
walk
around that.=