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From: "pinskia at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org> To: gcc-bugs@gcc.gnu.org Subject: [Bug target/112454] csinc (csel is though) is not being used when there is matches twice Date: Sat, 18 Nov 2023 06:48:49 +0000 [thread overview] Message-ID: <bug-112454-4-JZ3VvPFQ5P@http.gcc.gnu.org/bugzilla/> (raw) In-Reply-To: <bug-112454-4@http.gcc.gnu.org/bugzilla/> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112454 Andrew Pinski <pinskia at gcc dot gnu.org> changed: What |Removed |Added ---------------------------------------------------------------------------- Status|UNCONFIRMED |ASSIGNED Last reconfirmed| |2023-11-18 Ever confirmed|0 |1 Assignee|unassigned at gcc dot gnu.org |pinskia at gcc dot gnu.org --- Comment #2 from Andrew Pinski <pinskia at gcc dot gnu.org> --- Mine, looks like a cost issue not recording that 1 (and ~0) are free to create. you can see the cost issue if we look at combine for the case of 1 csel: Trying 37 -> 39: 37: r98:SI=0x1 39: r92:SI={(cc:CC!=0)?r100:SI:r98:SI} REG_DEAD r100:SI REG_DEAD cc:CC REG_DEAD r98:SI Successfully matched this instruction: (set (reg:SI 92 [ <retval> ]) (if_then_else:SI (ne (reg:CC 66 cc) (const_int 0 [0])) (reg:SI 100) (const_int 1 [0x1]))) allowing combination of insns 37 and 39 original costs 4 + 4 = 8 replacement cost 8 deferring deletion of insn with uid = 37. modifying insn i3 39: r92:SI={(cc:CC!=0)?r100:SI:0x1} REG_DEAD cc:CC REG_DEAD r100:SI deferring rescan insn with uid = 39. The replacement cost should be still 4.
next prev parent reply other threads:[~2023-11-18 6:48 UTC|newest] Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-11-09 6:54 [Bug target/112454] New: " pinskia at gcc dot gnu.org 2023-11-09 17:57 ` [Bug target/112454] " pinskia at gcc dot gnu.org 2023-11-18 6:48 ` pinskia at gcc dot gnu.org [this message] 2023-11-18 6:56 ` pinskia at gcc dot gnu.org 2023-11-26 23:52 ` pinskia at gcc dot gnu.org 2023-11-27 23:09 ` cvs-commit at gcc dot gnu.org
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