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From: "xry111 at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/112476] Unrecognizable insn with -O2 -march=la464 on
 loongarch64
Date: Sat, 11 Nov 2023 16:49:57 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D112476

Xi Ruoyao <xry111 at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
          Component|rtl-optimization            |target
             Status|NEW                         |ASSIGNED

--- Comment #4 from Xi Ruoyao <xry111 at gcc dot gnu.org> ---
The buggy nested subreg RTX is generated by LoongArch specific code
loongarch_expand_vec_cond_mask_expr.

Draft patch:

diff --git a/gcc/config/loongarch/loongarch.cc
b/gcc/config/loongarch/loongarch.cc
index d9b7a1076a2..0c7bafb5fb1 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -11197,7 +11197,9 @@ loongarch_expand_vec_cond_mask_expr (machine_mode m=
ode,
machine_mode vimode,
          if (mode !=3D vimode)
            {
              xop1 =3D gen_reg_rtx (vimode);
-             emit_move_insn (xop1, gen_rtx_SUBREG (vimode, operands[1], 0)=
);
+             emit_move_insn (xop1,
+                             simplify_gen_subreg (vimode, operands[1],
+                                                  mode, 0));
            }
          emit_move_insn (src1, xop1);
        }
@@ -11214,7 +11216,9 @@ loongarch_expand_vec_cond_mask_expr (machine_mode m=
ode,
machine_mode vimode,
          if (mode !=3D vimode)
            {
              xop2 =3D gen_reg_rtx (vimode);
-             emit_move_insn (xop2, gen_rtx_SUBREG (vimode, operands[2], 0)=
);
+             emit_move_insn (xop2,
+                             simplify_gen_subreg (vimode, operands[2],
+                                                  mode, 0));
            }
          emit_move_insn (src2, xop2);
        }
@@ -11233,7 +11237,8 @@ loongarch_expand_vec_cond_mask_expr (machine_mode m=
ode,
machine_mode vimode,
                          gen_rtx_AND (vimode, mask, src1));
       /* The result is placed back to a register with the mask.  */
       emit_insn (gen_rtx_SET (mask, bsel));
-      emit_move_insn (operands[0], gen_rtx_SUBREG (mode, mask, 0));
+      emit_move_insn (operands[0], simplify_gen_subreg (mode, mask,
+                                                       vimode, 0));
     }
 }=