[Bug target/112535] New: [14] RISC-V ICE: error: unable to find a register to spill during RTL pass: reload

[Bug target/112535] New: [14] RISC-V ICE: error: unable to find a register to spill during RTL pass: reload

[patrick at rivosinc dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112535

            Bug ID: 112535
           Summary: [14] RISC-V ICE: error: unable to find a register to
                    spill during RTL pass: reload
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: patrick at rivosinc dot com
  Target Milestone: ---

Created attachment 56587
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=56587&action=edit
-freport-bug output

> /scratch/tc-testing/tc-bisect-nov-7-2/build-rv64gc/bin/riscv64-unknown-linux-gnu-gcc -march=rv64gcv -mabi=lp64d -O2 red.c -freport-bug
red.c: In function 'g':
red.c:14:1: error: unable to find a register to spill
   14 | }
      | ^
red.c:14:1: error: this is the insn:
(insn 22 43 38 4 (set (mem:SI (subreg:DI (reg:V1DI 155 [orig:137 vect_a.17 ]
[137]) 0) [5 *_37+0 S4 A32])
        (const_int 0 [0])) "red.c":13:10 207 {*movsi_internal}
     (expr_list:REG_DEAD (reg:V1DI 155 [orig:137 vect_a.17 ] [137])
        (nil)))
during RTL pass: reload
red.c:14:1: internal compiler error: in lra_split_hard_reg_for, at
lra-assigns.cc:1861
0xa10e93 _fatal_insn(char const*, rtx_def const*, char const*, int, char
const*)
        ../../../gcc/gcc/rtl-error.cc:108
0x1073958 lra_split_hard_reg_for()
        ../../../gcc/gcc/lra-assigns.cc:1861
0x106d339 lra(_IO_FILE*)
        ../../../gcc/gcc/lra.cc:2495
0x1024119 do_reload
        ../../../gcc/gcc/ira.cc:5973
0x1024119 execute
        ../../../gcc/gcc/ira.cc:6161
Please submit a full bug report, with preprocessed source.
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.
Preprocessed source stored into /tmp/cc1ljSwT.out file, please attach this to
your bugreport

Testcase
int *a, *f;
char b, c;
int ***d;
static int ****e = &d;
void g() {
  c = 3;
  for (; c; c--)
    if (c < 8) {
      f = 0;
      ***e = a;
    }
  if (b)
    ***d = 0;
}

I have not attempted to bisect it yet.

-freport-bug output attached.

[Bug target/112535] [14 regression] RISC-V ICE: error: unable to find a register to spill during RTL pass: reload

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112535

--- Comment #1 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <panli@gcc.gnu.org>:

https://gcc.gnu.org/g:d85161a73b9bdd382e62ca1ba3f9f962971a9695

commit r14-5479-gd85161a73b9bdd382e62ca1ba3f9f962971a9695
Author: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date:   Wed Nov 15 15:15:08 2023 +0800

    RISC-V: Disallow RVV mode address for any load/store[PR112535]

    This patch is quite obvious patch which disallow for load/store address
register
    with RVV mode.

            PR target/112535

    gcc/ChangeLog:

            * config/riscv/riscv.cc (riscv_legitimate_address_p): Disallow RVV
modes base address.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/autovec/pr112535.c: New test.

[Bug target/112535] [14 regression] RISC-V ICE: error: unable to find a register to spill during RTL pass: reload

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112535

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |RESOLVED
         Resolution|---                         |FIXED
   Target Milestone|---                         |14.0

--- Comment #2 from Richard Biener <rguenth at gcc dot gnu.org> ---
Fixed I suppose.