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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/112597] RISC-V regression testsuite errors with
 rv64gcv_zvl256b
Date: Mon, 20 Nov 2023 13:54:50 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D112597

--- Comment #3 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <panli@gcc.gnu.org>:

https://gcc.gnu.org/g:a27f587816b6c3b8e46e4e46777abdc915ae00aa

commit r14-5624-ga27f587816b6c3b8e46e4e46777abdc915ae00aa
Author: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date:   Mon Nov 20 21:11:14 2023 +0800

    RISC-V: Fix intermediate mode on slide1 instruction for SEW64 on RV32

    This bug was discovered on PR112597, with -march=3Drv32gcv_zvl256b
--param=3Driscv-autovec-preference=3Dfixed-vlmax

    ICE:
    bug.c:10:1: error: unrecognizable insn:
       10 | }
          | ^
    (insn 10 9 11 2 (set (reg:V4SI 140)
            (unspec:V4SI [
                    (unspec:V4BI [
                            (const_vector:V4BI [
                                    (const_int 1 [0x1]) repeated x4
                                ])
                            (const_int 4 [0x4])
                            (const_int 2 [0x2]) repeated x3
                            (reg:SI 66 vl)
                            (reg:SI 67 vtype)
                        ] UNSPEC_VPREDICATE)
                    (unspec:V4SI [
                            (reg:SI 0 zero)
                        ] UNSPEC_VUNDEF)
                    (subreg:V4SI (reg:V2DI 138 [ v ]) 0)
                    (subreg:SI (reg/v:DI 136 [ b ]) 0)
                ] UNSPEC_VSLIDE1DOWN)) "bug.c":8:10 -1
         (nil))

    The rootcase is we don't enable V4SImode, instead, we already have RVVM=
F2SI
which is totally same as V4SI
    on -march=3Drv32gcv_zvl256 + --param=3Driscv-autovec-preference=3Dfixed=
-vlmax.

    The attribute VDEMODE map to V4SI is incorrect, we remove attributes and
use get_vector_mode to get
    right mode.

            PR target/112597

    gcc/ChangeLog:

            * config/riscv/vector-iterators.md: Remove VDEMOTE and VMDEMOTE.
            * config/riscv/vector.md: Fix slide1 intermediate mode bug.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/autovec/pr112597-1.c: New test.=