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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/112598] RISC-V regression testsuite errors with
 rv64gcv_zvl512b
Date: Tue, 21 Nov 2023 13:38:53 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D112598

--- Comment #3 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <panli@gcc.gnu.org>:

https://gcc.gnu.org/g:8faae311a60a552ed3d506de28c50c77fa49b229

commit r14-5677-g8faae311a60a552ed3d506de28c50c77fa49b229
Author: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date:   Tue Nov 21 18:02:09 2023 +0800

    RISC-V: Disallow COSNT_VECTOR for DI on RV32

    This bug is exposed when testing on zvl512b RV32 system.

    The rootcause is RA reload DI CONST_VECTOR into vmv.v.x then it ICE.

    So disallow DI CONST_VECTOR on RV32.

            PR target/112598

    gcc/ChangeLog:

            * config/riscv/riscv.cc (riscv_const_insns): Disallow DI
CONST_VECTOR on RV32.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/autovec/pr112598-1.c: New test.=