From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id C26723858018; Mon, 27 Nov 2023 11:37:23 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org C26723858018 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1701085043; bh=VgYVTlGD2C3oYqhl63C9vTE5LZ3wfNdXHZkzoLk0rj0=; h=From:To:Subject:Date:In-Reply-To:References:From; b=l5BlaEHQ1Y3h1n76yVGfP9oXTCayHqHP/M0cc08U+GqG8YqujOYIObSu77NbRs6KY GAPAnNwVHR3wxw+4HRYHTnsn6JCnUHhVEg96nnmS9kyzguWe4iZQ/bN4w6Zx2mImO5 7WRmghGw7QI7K4wcekewqMKJe5Y6+sACD5pwA6Mo= From: "pan2.li at intel dot com" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/112598] RISC-V regression testsuite errors with rv64gcv_zvl512b Date: Mon, 27 Nov 2023 11:37:22 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 14.0 X-Bugzilla-Keywords: testsuite-fail X-Bugzilla-Severity: normal X-Bugzilla-Who: pan2.li at intel dot com X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D112598 --- Comment #14 from Li Pan --- The below diff similar to the x86 workaround looks not working, unless we change the `+m` to `=3Dm`. But I don't fully test the impact of this change except the case itself. diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 935eeb7fd8e..882fc8fe5ec 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -85,6 +85,9 @@ (define_c_enum "unspec" [ ;; String unspecs UNSPEC_STRLEN + + ;; test + UNSPEC_MASKSTORE ]) (define_c_enum "unspecv" [ diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index ba9c9e5a9b6..2f74cec51d1 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -1738,16 +1738,17 @@ (define_insn_and_split "*pred_mov" ;; Dedicated pattern for vse.v instruction since we can't reuse pred_mov pattern to include ;; memory operand as input which will produce inferior codegen. (define_insn "@pred_store" - [(set (match_operand:V 0 "memory_operand" "+m") - (if_then_else:V - (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1") - (match_operand 3 "vector_length_operand" " rK") - (match_operand 4 "const_int_operand" " i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operand:V 2 "register_operand" " vr") - (match_dup 0)))] + [(set (match_operand:V 0 "memory_operand" "=3Dm") + (unspec:V + [(if_then_else:V + (unspec: + [(match_operand: 1 "vector_mask_operand" "vmWc1") + (match_operand 3 "vector_length_operand" " rK") + (match_operand 4 "const_int_operand" " i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (match_operand:V 2 "register_operand" " vr") + (match_dup 0))] UNSPEC_MASKSTORE))] "TARGET_VECTOR" "vse.v\t%2,%0%p1" [(set_attr "type" "vste")=