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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/112599] RISC-V regression testsuite errors with rv64gcv_zvl1024b
Date: Thu, 23 Nov 2023 12:09:08 +0000 [thread overview]
Message-ID: <bug-112599-4-KXttWiHFam@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-112599-4@http.gcc.gnu.org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112599
--- Comment #3 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Robin Dapp <rdapp@gcc.gnu.org>:
https://gcc.gnu.org/g:35a688f434159a923420310860c5bc721e29a741
commit r14-5777-g35a688f434159a923420310860c5bc721e29a741
Author: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date: Thu Nov 23 19:59:52 2023 +0800
RISC-V: Disable AVL propagation of vrgather instruction
This patch fixes following FAILs in zvl1024b of both RV32/RV64:
FAIL: gcc.c-torture/execute/990128-1.c -O2 execution test
FAIL: gcc.c-torture/execute/990128-1.c -O2 -flto -fno-use-linker-plugin
-flto-partition=none execution test
FAIL: gcc.c-torture/execute/990128-1.c -O2 -flto -fuse-linker-plugin
-fno-fat-lto-objects execution test
FAIL: gcc.c-torture/execute/990128-1.c -O3 -fomit-frame-pointer
-funroll-loops -fpeel-loops -ftracer -finline-functions execution test
FAIL: gcc.c-torture/execute/990128-1.c -O3 -g execution test
FAIL: gcc.dg/torture/pr58955-2.c -O3 -fomit-frame-pointer -funroll-loops
-fpeel-loops -ftracer -finline-functions execution test
The root case can be simpliy described in this following small case:
https://godbolt.org/z/7GaxbEGzG
typedef int64_t v1024b __attribute__ ((vector_size (128)));
void foo (void *out, void *in, int64_t a, int64_t b)
{
v1024b v = {a,a,a,a,a,a,a,a,a,a,a,a,a,a,a,a};
v1024b v2 = {b,b,b,b,b,b,b,b,b,b,b,b,b,b,b,b};
v1024b index = *(v1024b*)in;
v1024b v3 = __builtin_shuffle (v, v2, index);
__riscv_vse64_v_i64m1 (out, (vint64m1_t)v3, 10);
}
Incorrect ASM:
foo:
li a5,31
vsetivli zero,10,e64,m1,ta,mu
vmv.v.x v2,a5
vl1re64.v v1,0(a1)
vmv.v.x v4,a2
vand.vv v1,v1,v2
vmv.v.x v3,a3
vmsgeu.vi v0,v1,16
vrgather.vv v2,v4,v1 --> AVL = VLMAX according to codes.
vadd.vi v1,v1,-16
vrgather.vv v2,v3,v1,v0.t --> AVL = VLMAX according to codes.
vse64.v v2,0(a0) --> AVL = 10 according to codes.
ret
For vrgather dest, source, index instruction, when index may has the value
> the following store AVL
that is index value > 10. In this situation, the codes above will end up
with:
The source vector of vrgather has undefined value on index >= AVL (which is
10 in this case).
So disable AVL propagation for vrgather instruction.
PR target/112599
PR target/112670
gcc/ChangeLog:
* config/riscv/riscv-avlprop.cc (alv_can_be_propagated_p): New
function.
(vlmax_ta_p): Disable vrgather AVL propagation.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/pr112599-1.c: New test.
next prev parent reply other threads:[~2023-11-23 12:09 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-17 21:19 [Bug target/112599] New: " patrick at rivosinc dot com
2023-11-17 21:21 ` [Bug target/112599] " patrick at rivosinc dot com
2023-11-21 17:47 ` patrick at rivosinc dot com
2023-11-23 12:09 ` cvs-commit at gcc dot gnu.org [this message]
2023-11-24 6:34 ` cvs-commit at gcc dot gnu.org
2023-11-26 9:15 ` cvs-commit at gcc dot gnu.org
2023-11-27 17:57 ` patrick at rivosinc dot com
2023-12-04 21:41 ` patrick at rivosinc dot com
2023-12-11 23:59 ` patrick at rivosinc dot com
2024-01-24 23:53 ` patrick at rivosinc dot com
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