From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 92EA43858D38; Wed, 22 Nov 2023 01:54:24 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 92EA43858D38 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1700618064; bh=jz+HnsuYRQyJaII0mvjDkb80rFAKjifEOVXuBDberpA=; h=From:To:Subject:Date:In-Reply-To:References:From; b=ry/LCaUlQ0dk3Y7DhEaO0sdLqq1DlZWDAElBv/wCXk0APVBsQfmprEJ5+xtqZNLEs cU8cqCdP1GeiC1IHIpQJMY/nMuwft6OeRnJK2uz863ZCN7Jfensk7rChNvUuPzHrls 62hfOmo7/fb+yet+X+yprYSweXf/Ub1xoqjiYNtM= From: "haochen.jiang at intel dot com" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/112643] [14 regression] including x86intrin.h is broken for -march=native (which adds -mno-avx10.1-256 ) Date: Wed, 22 Nov 2023 01:54:22 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 14.0 X-Bugzilla-Keywords: build, rejects-valid X-Bugzilla-Severity: normal X-Bugzilla-Who: haochen.jiang at intel dot com X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: 14.0 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D112643 --- Comment #21 from Haochen Jiang --- (In reply to Andrew Pinski from comment #20) > The use of __builtin_ia32_2intersectd128 in avx512vp2intersectvlintrin.h = has: > #pragma GCC target("avx512vp2intersect,avx512vl,no-evex512") >=20 > While i386-builtin.def does: > BDESC (0, OPTION_MASK_ISA2_AVX512VP2INTERSECT, CODE_FOR_nothing, > "__builtin_ia32_2intersectd128", IX86_BUILTIN_2INTERSECTD128, UNKNOWN, (i= nt) > VOID_FTYPE_PUQI_PUQI_V4SI_V4SI) This is a known issue I figured out yesterday but should not cause the prob= lem since it actually relaxed conditions. It will cause ICE when caliing builti= ns directly. The reason why I am not reproducing the regression seems mainly caused by t= he machine I built with all have AVX512, but all the CPUs mentioned here did n= ot, which will lead to different behavior on march and option override. Rebuilding on AVX only machine to reproduce.=