From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 2FDC63858431; Fri, 24 Nov 2023 11:13:21 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 2FDC63858431 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1700824401; bh=4PqJ8834d+8RdrBCKNu8tV1J52dsUJxTQU/BC1w8fjU=; h=From:To:Subject:Date:In-Reply-To:References:From; b=EukutuA9nx1b2PSgAZdAyHz8/vqIbexn8KfacXfgGxeb7qVi681xUL6NrSf6czGbx hj3vqszvw4ZL4Ei6wxTedaP3FGBLqxmkuOtB1CpKKNrRLTb6iDlsWxd+tXCD4ZX+nV vDko4yPwC73x+c6OpQhrYPK8K2z0tm6l9pA6e1OA= From: "cvs-commit at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/112681] [14 Regression] ICE: in extract_insn, at recog.cc:2804 (unrecognizable insn) with -O2 -mfma -mno-sse4.2 and memcmp() since r14-5747 Date: Fri, 24 Nov 2023 11:13:19 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 14.0 X-Bugzilla-Keywords: ice-on-valid-code X-Bugzilla-Severity: normal X-Bugzilla-Who: cvs-commit at gcc dot gnu.org X-Bugzilla-Status: ASSIGNED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: jakub at gcc dot gnu.org X-Bugzilla-Target-Milestone: 14.0 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D112681 --- Comment #8 from CVS Commits --- The master branch has been updated by Jakub Jelinek : https://gcc.gnu.org/g:3eb9cae6d375d222787498b15ac87f383b3834fe commit r14-5822-g3eb9cae6d375d222787498b15ac87f383b3834fe Author: Jakub Jelinek Date: Fri Nov 24 12:12:20 2023 +0100 i386: Fix ICE during cbranchv16qi4 expansion [PR112681] The following testcase ICEs, because cbranchv16qi4 expansion calls ix86_expand_branch with op1 being a pre-AVX unaligned memory and ix86_expand_branch emits a xorv16qi3 instruction without making sure the operand predicates are satisfied. While I could manually check if the argument (or both?) doesn't match vector_operand predicate (apparently this one or bcst_vector_oper= and is used in all integral 16+ bytes *xorv*3 instructions) force it into a register, but as all gen_xorv*3 expanders call ix86_expand_vector_logical_operator, it seems easier to just call that function which ensures the right thing happens. Calling the individual gen_xorv*3 functions would mean ugly switch on the modes and using high level expand_simple_binop here seems too high level to me. 2023-11-24 Jakub Jelinek PR target/112681 * config/i386/i386-expand.cc (ix86_expand_branch): Use ix86_expand_vector_logical_operator to expand vector XOR rather than gen_rtx_SET on gen_rtx_XOR. * gcc.target/i386/sse4-pr112681.c: New test.=