From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 721203858CD1; Thu, 23 Nov 2023 19:46:46 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 721203858CD1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1700768806; bh=locLXrKmZC9vhg2Gf1IKWkC1ynFN35Jebz7mUTLL0bw=; h=From:To:Subject:Date:In-Reply-To:References:From; b=V7D1Mgqm0iue2H/T6gd1XprTO/Ba7lFEpoYgBFNyAHQLxm+tv+ilZb96GXayUJkTu KR2MByhgiIS80AkShp5LuDQiI+B8su/AnUGoexQI5+s389rj8PAH4KEqv5Q+VCkWvO 6dVVF9vpcV+GzMZXZUTTs+648JdXtD8midVqhU8c= From: "jakub at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/112681] [14 Regression] ICE: in extract_insn, at recog.cc:2804 (unrecognizable insn) with -O2 -mfma -mno-sse4.2 and memcmp() since r14-5747 Date: Thu, 23 Nov 2023 19:46:46 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 14.0 X-Bugzilla-Keywords: ice-on-valid-code X-Bugzilla-Severity: normal X-Bugzilla-Who: jakub at gcc dot gnu.org X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: 14.0 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D112681 --- Comment #4 from Jakub Jelinek --- Flags can be just -O2 -msse4.1 -mno-sse4.2 as well or even -O2 -msse4.2 -mno-avx. --- gcc/config/i386/i386-expand.cc.jj 2023-11-21 09:31:35.792395304 +0100 +++ gcc/config/i386/i386-expand.cc 2023-11-23 20:43:51.675586034 +0100 @@ -2453,6 +2453,8 @@ ix86_expand_branch (enum rtx_code code, /* Generate XOR since we can't check that one operand is zero vector. */ tmp =3D gen_reg_rtx (mode); + if (!vector_operand (op1, mode)) + op1 =3D force_reg (mode, op1); emit_insn (gen_rtx_SET (tmp, gen_rtx_XOR (mode, op0, op1))); tmp =3D gen_lowpart (p_mode, tmp); emit_insn (gen_rtx_SET (gen_rtx_REG (CCZmode, FLAGS_REG), seems to fix it.=