[Bug rtl-optimization/112758] [13/14 Regression] Inconsistent Bitwise AND Operation Result between int and long long int

["jakub at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112758

Jakub Jelinek <jakub at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |ebotcazou at gcc dot gnu.org,
                   |                            |jakub at gcc dot gnu.org,
                   |                            |law at gcc dot gnu.org,
                   |                            |segher at gcc dot gnu.org

--- Comment #3 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
Seems expand_compound_operation is called on
(sign_extend:DI (mem/c:SI (lo_sum:DI (reg/f:DI 144)
            (symbol_ref:DI ("globalVar") [flags 0x86] <var_decl 0x7fffea1f9b40
globalVar>)) [1 globalVar+0 S4 A32]))
and takes the
7336          tem = gen_lowpart (mode, XEXP (x, 0));
7337          if (!tem || GET_CODE (tem) == CLOBBER)
7338            return x;
7339          tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
7340                                      tem, modewidth - pos - len);
7341          tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT :
ASHIFTRT,
7342                                      mode, tem, modewidth - len);
path on it, mode being DImode, modewidth 64, pos 0, len 32.
The second simplify_shift_const is then called with
(ashift:DI (subreg:DI (mem/c:SI (lo_sum:DI (reg/f:DI 144)
                (symbol_ref:DI ("globalVar") [flags 0x86] <var_decl
0x7fffea1f9b40 globalVar>)) [1 globalVar+0 S4 A32]) 0)
    (const_int 32 [0x20]))
and triggers the
10810                 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has
more
10811                    than C1 high-order bits equal to the sign bit, we can
convert
10812                    this to either an ASHIFT or an ASHIFTRT depending on
the
10813                    two counts.
10814   
10815                    We cannot do this if VAROP's mode is not
SHIFT_UNIT_MODE.  */
10816   
10817                 if (code == ASHIFTRT && first_code == ASHIFT
10818                     && int_varop_mode == shift_unit_mode
10819                     && (num_sign_bit_copies (XEXP (varop, 0),
shift_unit_mode)
10820                         > first_count))
10821                   {
10822                     varop = XEXP (varop, 0);
10823                     count -= first_count;
10824                     if (count < 0)
10825                       {
10826                         count = -count;
10827                         code = ASHIFT;
10828                       }
10829   
10830                     continue;
10831                   }
optimization in there.
As RISC V is WORD_REGISTER_OPERATIONS target with load_extend_op (E_SImode) ==
SIGN_EXTEND, it triggers the:
5444              /* For paradoxical SUBREGs on machines where all register
operations
5445                 affect the entire register, just look inside.  Note that
we are
5446                 passing MODE to the recursive call, so the number of sign
bit
5447                 copies will remain relative to that mode, not the inner
mode.
5448    
5449                 This works only if loads sign extend.  Otherwise, if we
get a
5450                 reload for the inner part, it may be loaded from the
stack, and
5451                 then we lose all sign bit copies that existed before the
store
5452                 to the stack.  */
5453              if (WORD_REGISTER_OPERATIONS
5454                  && load_extend_op (inner_mode) == SIGN_EXTEND
5455                  && paradoxical_subreg_p (x)
5456                  && MEM_P (SUBREG_REG (x)))
5457                return cached_num_sign_bit_copies (SUBREG_REG (x), mode,
5458                                                   known_x, known_mode,
known_ret);
path and so the sign-extension in the end folds into just a paradoxical subreg
of the MEM.  But probably something in the combiner then just sees a
paradoxical SUBREG and thinks that all the bits above the SUBREG_REG are
undefined and picks ZERO_EXTEND.
I'm afraid I don't know enough about WORD_REGISTER_OPERATIONS to know what is
right and what is not.