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From: "segher at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug rtl-optimization/112758] [13/14 Regression] Inconsistent
 Bitwise AND Operation Result between int and long long int
Date: Sat, 09 Dec 2023 19:25:24 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D112758

--- Comment #10 from Segher Boessenkool <segher at gcc dot gnu.org> ---
(In reply to Jakub Jelinek from comment #6)
> I must say I have no idea what WORD_REGISTER_OPERATION says about the upp=
er
> bits of a paradoxical SUBREG if it is a MEM and load_extend_op (inner_mod=
e)
> is ZERO_EXTEND (zeros then?  Then this optimization is ok), or something
> else?  And what it says on REGs.

It says those upper bits are well-defined, i.e. whatever MD pattern is used=
 for
it eventually will emit machine code that has the exact same result for tho=
se
upper bits.  This is almost impossible to prove for any non-trivial target,=
 and
certainly extremely fragile.=