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From: "ebotcazou at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug rtl-optimization/112758] [13/14 Regression] Inconsistent
 Bitwise AND Operation Result between int and long long int
Date: Sat, 09 Dec 2023 08:51:16 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D112758

--- Comment #7 from Eric Botcazou <ebotcazou at gcc dot gnu.org> ---
> I must say I have no idea what WORD_REGISTER_OPERATION says about the upp=
er
> bits of a paradoxical SUBREG if it is a MEM and load_extend_op (inner_mod=
e)
> is ZERO_EXTEND (zeros then?

Yes.

> Then this optimization is ok), or something else?  And what it says on RE=
Gs.

That it contains the result of the operation that was applied to the SUBREG=
 as
if it was applied to the entire REG, provided that word_register_operation_=
p is
true.  Otherwise, it's undefined.=