From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 5BA003858CD1; Fri, 8 Dec 2023 19:36:10 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 5BA003858CD1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1702064170; bh=goXu5LZ83i174JaaFS4T7/nSPKZBqhVSw4Yx9tv2e0c=; h=From:To:Subject:Date:In-Reply-To:References:From; b=CsIxaQdmYdRSZJiLlZ2uw8TNhiPCpHyDG13vSpD3PPZf7gpCnH8SduQHuopMgCZaf ncpkj5fY3TjVe78paPYRkNXwUWqhWtWlAF8nfXPJ9CDuAwLTl3lWicNNO0rBe97vb+ aoYtC7f/eIwNDEsJb9vcg2NNAphDgnn7K+roJyVc= From: "jakub at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug rtl-optimization/112758] [13/14 Regression] Inconsistent Bitwise AND Operation Result between int and long long int Date: Fri, 08 Dec 2023 19:36:10 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: rtl-optimization X-Bugzilla-Version: 14.0 X-Bugzilla-Keywords: needs-bisection, wrong-code X-Bugzilla-Severity: normal X-Bugzilla-Who: jakub at gcc dot gnu.org X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: 13.3 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D112758 --- Comment #6 from Jakub Jelinek --- I must say I have no idea what WORD_REGISTER_OPERATION says about the upper bits of a paradoxical SUBREG if it is a MEM and load_extend_op (inner_mode)= is ZERO_EXTEND (zeros then? Then this optimization is ok), or something else?= =20 And what it says on REGs.=