From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id A164138708D0; Thu, 21 Dec 2023 20:06:56 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A164138708D0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1703189216; bh=RDFS+JHwuMUDccq6ynNM6WE7aHDBCIE/RC1xXril3ew=; h=From:To:Subject:Date:In-Reply-To:References:From; b=LG2FHxkitJz+IBG5TwnW7QUCZEM2RDsZOvJ3NiVTvWsKM8NHaxT0ogyxI8Z/jnSec QfUIIbrW+9L+ZD3RUJ/T+GAt8G0uY4RpVqOX9HaNg4fC3cXZCRymKjY21XVFXmwjsH SkgD+ylx+9juAmo0gTNKznRZAAfFmh9VaCa2d2N0= From: "jakub at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug rtl-optimization/112758] [13/14 Regression] Inconsistent Bitwise AND Operation Result between int and long long int Date: Thu, 21 Dec 2023 20:06:56 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: rtl-optimization X-Bugzilla-Version: 14.0 X-Bugzilla-Keywords: needs-bisection, wrong-code X-Bugzilla-Severity: normal X-Bugzilla-Who: jakub at gcc dot gnu.org X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: 13.3 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D112758 --- Comment #16 from Jakub Jelinek --- Here is what I'd propose, but I can't really test it on any WORD_REGISTER_OPERATIONS target. 2023-12-21 Jakub Jelinek PR rtl-optimization/112758 * combine.cc (make_compopund_operation_int): Optimize AND of a SUBR= EG based on nonzero_bits of SUBREG_REG and constant mask on WORD_REGISTER_OPERATIONS targets only if it is a zero extending MEM load. * gcc.c-torture/execute/pr112758.c: New test. --- gcc/combine.cc.jj 2023-12-11 23:52:03.528513943 +0100 +++ gcc/combine.cc 2023-12-21 20:25:45.461737423 +0100 @@ -8227,12 +8227,20 @@ make_compound_operation_int (scalar_int_ int sub_width; if ((REG_P (sub) || MEM_P (sub)) && GET_MODE_PRECISION (sub_mode).is_constant (&sub_width) - && sub_width < mode_width) + && sub_width < mode_width + && (!WORD_REGISTER_OPERATIONS + || sub_width >=3D BITS_PER_WORD + /* On WORD_REGISTER_OPERATIONS targets the bits + beyond sub_mode aren't considered undefined, + so optimize only if it is a MEM load when MEM loads + zero extend, because then the upper bits are all zero.= */ + || (MEM_P (sub) + && load_extend_op (sub_mode) =3D=3D ZERO_EXTEND))) { unsigned HOST_WIDE_INT mode_mask =3D GET_MODE_MASK (sub_mode); unsigned HOST_WIDE_INT mask; - /* original AND constant with all the known zero bits set */ + /* Original AND constant with all the known zero bits set. */ mask =3D UINTVAL (XEXP (x, 1)) | (~nonzero_bits (sub, sub_mod= e)); if ((mask & mode_mask) =3D=3D mode_mask) { --- gcc/testsuite/gcc.c-torture/execute/pr112758.c.jj 2023-12-21 21:01:43.780755959 +0100 +++ gcc/testsuite/gcc.c-torture/execute/pr112758.c 2023-12-21 21:01:30.521940358 +0100 @@ -0,0 +1,15 @@ +/* PR rtl-optimization/112758 */ + +int a =3D -__INT_MAX__ - 1; + +int +main () +{ + if (-__INT_MAX__ - 1U =3D=3D 0x80000000ULL) + { + unsigned long long b =3D 0xffff00ffffffffffULL; + if ((b & a) !=3D 0xffff00ff80000000ULL) + __builtin_abort (); + } + return 0; +}=