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From: "jakub at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug rtl-optimization/112758] [13/14 Regression] Inconsistent
 Bitwise AND Operation Result between int and long long int
Date: Sat, 09 Dec 2023 09:11:51 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D112758

--- Comment #8 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
(In reply to Eric Botcazou from comment #7)
> > I must say I have no idea what WORD_REGISTER_OPERATION says about the u=
pper
> > bits of a paradoxical SUBREG if it is a MEM and load_extend_op (inner_m=
ode)
> > is ZERO_EXTEND (zeros then?
>=20
> Yes.
>=20
> > Then this optimization is ok), or something else?  And what it says on =
REGs.
>=20
> That it contains the result of the operation that was applied to the SUBR=
EG
> as if it was applied to the entire REG, provided that
> word_register_operation_p is true.  Otherwise, it's undefined.

But if we see a REG in there, we don't really know what operation it was.
Sure, if the operation is visible, we know it, but say PLUS can be extended
either way.

Which means punt on this optimization for WORD_REGISTER_OPERATIONS if the o=
uter
mode is word_mode, except when sub is a MEM and load_extend_op (inner_mode)=
 =3D=3D
ZERO_EXTEND?=