From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 0C7A43858C98; Sat, 9 Dec 2023 22:06:51 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 0C7A43858C98 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1702159611; bh=gi4xrTWy9tFu5oUz2DJmQgWCUgFuJFwPoxglL22qsuA=; h=From:To:Subject:Date:In-Reply-To:References:From; b=TjRtO7h++3YBEyomZjCM6i5nUv8Dtoph0eAdkBpFCOVbPFR1IUdA8i1RXLPZ2nlt0 oVDmVp7SiffIRvZtE0As5FAdwfvQm+MhaoQ7fDClvlbexLdutKj4m1yh39n+y6KPf/ tJnLN8PqGu7sYOX8G5SB4O2mP+vFv7gbp/1oh/pU= From: "ebotcazou at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug rtl-optimization/112758] [13/14 Regression] Inconsistent Bitwise AND Operation Result between int and long long int Date: Sat, 09 Dec 2023 22:06:50 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: rtl-optimization X-Bugzilla-Version: 14.0 X-Bugzilla-Keywords: needs-bisection, wrong-code X-Bugzilla-Severity: normal X-Bugzilla-Who: ebotcazou at gcc dot gnu.org X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: 13.3 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D112758 --- Comment #11 from Eric Botcazou --- > It says those upper bits are well-defined, i.e. whatever MD pattern is us= ed > for it eventually will emit machine code that has the exact same result f= or > those upper bits. No, that's not true, the set of "register operations" is restricted.=