From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 62E0A3858C62; Fri, 1 Dec 2023 12:07:51 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 62E0A3858C62 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1701432471; bh=um25DPwArgdCS7q6boTALS5S6n2kJsVLpo9N9FJ+27M=; h=From:To:Subject:Date:In-Reply-To:References:From; b=Qz+uNVE6aHz8yE8zY0aIAdYwVb0EkI4wTRliFEMr5DLpLS+mCIEpBF0KdseZAI/Sv Ee+4flcnxGBK0SqBPcl7bPmgLZIu3gdTvO4MrwmAvkCYf81qy44cvInnW9sRRMSj0W W6gmUiiL0KMXqxNkm2PiwVmibUTk3MyOLkmXt9LU= From: "rguenth at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/112773] [14 Regression] RISC-V ICE: in force_align_down_and_div, at poly-int.h:1828 on rv32gcv_zvl256b Date: Fri, 01 Dec 2023 12:07:50 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 14.0 X-Bugzilla-Keywords: X-Bugzilla-Severity: normal X-Bugzilla-Who: rguenth at gcc dot gnu.org X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: 14.0 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: everconfirmed bug_status cf_reconfirmed_on Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D112773 Richard Biener changed: What |Removed |Added ---------------------------------------------------------------------------- Ever confirmed|0 |1 Status|UNCONFIRMED |NEW Last reconfirmed| |2023-12-01 --- Comment #10 from Richard Biener --- The issue might be we do not use vec_extract for memory arguments: /* Use vec_extract patterns for extracting parts of vectors whenever available. If that fails, see whether the current modes and bitregion give a natural subreg. */=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20 machine_mode outermode =3D GET_MODE (op0); if (VECTOR_MODE_P (outermode) && !MEM_P (op0)) {=20=20=20 and somehow the original reg operand got spilled inbetween. That happens here, after we could make vec_extract work for this. /* Make sure we are playing with integral modes. Pun with subregs if we aren't. */ opt_scalar_int_mode op0_mode =3D int_mode_for_mode (GET_MODE (op0)); scalar_int_mode imode; if (!op0_mode.exists (&imode) || imode !=3D GET_MODE (op0)) {=20 ... else { poly_int64 size =3D GET_MODE_SIZE (GET_MODE (op0)); rtx mem =3D assign_stack_temp (GET_MODE (op0), size); emit_move_insn (mem, op0); op0 =3D adjust_bitfield_address_size (mem, BLKmode, 0, size); } now, if we spilled we can elide the round-down I think (which is for the fear of accessing invalid memory). Thus like the following? diff --git a/gcc/expmed.cc b/gcc/expmed.cc index b294eabb08d..e2b38b87bdf 100644 --- a/gcc/expmed.cc +++ b/gcc/expmed.cc @@ -1856,7 +1856,7 @@ extract_bit_field_1 (rtx str_rtx, poly_uint64 bitsize, poly_uint64 bitnum, /* If we have a memory source and a non-constant bit offset, restrict the memory to the referenced bytes. This is a worst-case fallback but is useful for things like vector booleans. */ - if (MEM_P (op0) && !bitnum.is_constant ()) + if (MEM_P (str_rtx) && !bitnum.is_constant ()) { bytenum =3D bits_to_bytes_round_down (bitnum); bitnum =3D num_trailing_bits (bitnum); but that defers the ICE to during RTL pass: expand t.c: In function 'e': t.c:4:6: internal compiler error: in to_constant, at poly-int.h:588 4 | void e(unsigned f) { | ^ 0x10ea530 poly_int<2u, unsigned long>::to_constant() const /home/rguenther/src/trunk/gcc/poly-int.h:588 0x13cec67 extract_bit_field_1 /home/rguenther/src/trunk/gcc/expmed.cc:1872 so I guess we really need to match the vec_extract pattern. So you need to debug why that doesn't match here.=